LSI LSI53C896, Technical Manual

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PCI Functional Description 2-3
2.1.1 PCI Addressing
There are three physical PCI-defined address spaces:
•
PCI Configuration Space .
•
I/O Space for operating registers.
•
Memory Space for operating registers.
2.1.1.1 Configuration Space
The host processor uses this configuration space to initialize the
LSI53C896. Two independent sets of configuration space registers are
defined, one set for each SCSI function. The Configuration registers are
accessible only by system BIOS during PCI configuration cycles. Each
configuration space is a contiguous 256 X 8-bit set of addresses.
Decoding C_BE[3:0]/ determines if a PCI cycle is intended to access the
configuration register space. The IDSEL bus signal is a “chip select” that
allows access to the configuration register space only. A configuration
read/write cycle without IDSEL is ignored. The eight lower order address
bits (AD[7:0]) are used to select a specific 8-bit register. Since the
LSI53C896 is a PCI multifunction device, bits AD[10:8] decode either
SCSI Function A Configuration register (AD[10:8] = 0b000) or SCSI
Function B Configuration register (AD[10:8] = 0b001).
At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C896, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C896 compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If there is a match of
the upper 24 bits, the access is for the LSI53C896 and the low-order
eight bits define the register to be accessed. A decode of C_BE[3:0]/
determines which registers and what type of access is to be performed.
2.1.1.2 I/O Space
The PCI specification defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the LSI53C896.
Base Address Register Zero (I/O) determines which 256-byte I/O area
this device occupies.
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