LSI LSI53C896, Technical Manual

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2-32 Functional Description
Figure 2.4 LSI53C896 Host Interface SCSI Data Paths
The following items determine if any bytes remain in the data path when
the chip halts an operation:
Asynchronous SCSI Send –
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test
Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test
Five (CTEST5) register is set), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between zero and 944.
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the
PCI Interface
DMA FIFO
(8 Bytes x 118)
SODL Register
SCSI Interface
PCI Interface
DMA FIFO
(8 Bytes x 118)
SIDL Register
SCSI Interface
PCI Interface
DMA FIFO
(8 Bytes x 118)
SODL Register
SCSI Interface
SODR Register
PCI Interface
DMA FIFO
(8 Bytes x 118)
SCSI Interface
SCSI FIFO
(1 or 2 Bytes x 31)
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
SWIDE Register
SWIDE Register
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