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5-12

SCSI SCRIPTS Instruction Set

If the SCSI phase bits match the value stored in the

Status One (SSTAT1)

register, the LSI53C896 transfers

the number of bytes specified in the

DMA Byte Counter

register starting at the address pointed to by the

DMA Next Address (DNAD)

register. If the opcode bit is

cleared and a data transfer ends on an odd byte
boundary, the LSI53C896 stores the last byte in the

Wide Residue (SWIDE)

register during a receive

operation, or in the

SCSI Output Data Latch (SODL)

register during a send operation. This byte is combined
with the first byte from the subsequent transfer so that a
wide transfer can complete.

If the SCSI phase bits do not match the value stored in
the

SCSI Status One (SSTAT1)

register, the LSI53C896

generates a phase mismatch interrupt and the instruction
is not executed.

During a Message-Out phase, after the LSI53C896 has
performed a select with Attention (or SATN/ is manually
asserted with a Set ATN instruction), the LSI53C896
deasserts SATN/ during the final SREQ/SACK/
handshake.

When the LSI53C896 is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the SACK/
signal using the Clear SACK I/O instruction.

SCSIP[2:0]

SCSI Phase

[26:24]

This 3-bit field defines the desired SCSI information
transfer phase. When the LSI53C896 operates in the
initiator mode, these bits are compared with the latched
SCSI phase bits in the

SCSI Status One (SSTAT1)

register. When the LSI53C896 operates in the target
mode, it asserts the phase defined in this field. The
following table describes the possible combinations and
the corresponding SCSI phase.

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Summary of Contents for LSI53C896

Page 1: ...LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller TECHNICAL MANUAL A p r i l 2 0 0 1 Version 3 2...

Page 2: ...ny products herein at any time without notice LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein except as expressly agreed...

Page 3: ...ocument has the following chapters and appendixes Chapter 1 Introduction describes the general information about the LSI53C896 Chapter 2 Functional Description describes the main functional areas of t...

Page 4: ...CO 80112 800 854 7179 or 303 397 7956 outside U S FAX 303 397 2740 Ask for document number X3 131 1994 SCSI 2 X3 253 SCSI 3 Parallel Interface ENDL Publications 14426 Black Walnut Court Saratoga CA 95...

Page 5: ...ata Contains Signal Descriptions Registers and Mechanical Drawings 0 6 10 22 97 First Draft Added Introduction Functional Description SCSI SCRIPTS Instruction Set Electrical Characteristics Register S...

Page 6: ...vi Preface...

Page 7: ...5 6 Reliability 1 9 1 5 7 Testability 1 10 Chapter 2 Functional Description 2 1 PCI Functional Description 2 2 2 1 1 PCI Addressing 2 3 2 1 2 PCI Bus Commands and Functions Supported 2 4 2 1 3 Intern...

Page 8: ...2 59 2 5 Power Management 2 59 2 5 1 Power State D0 2 60 2 5 2 Power State D1 2 61 2 5 3 Power State D2 2 61 2 5 4 Power State D3 2 61 Chapter 3 Signal Descriptions 3 1 Internal Pull ups on LSI53C896...

Page 9: ...4 5 2 3 Third Dword 5 14 5 3 I O Instructions 5 15 5 3 1 First Dword 5 15 5 3 2 Second Dword 5 22 5 4 Read Write Instructions 5 23 5 4 1 First Dword 5 23 5 4 2 Second Dword 5 24 5 4 3 Read Modify Writ...

Page 10: ...gures 1 1 Typical LSI53C896 System Application 1 2 1 2 Typical LSI53C896 Board Application 1 3 2 1 LSI53C896 Block Diagram 2 2 2 2 Parity Checking Generation 2 30 2 3 DMA FIFO Sections 2 31 2 4 LSI53C...

Page 11: ...6 5 Hysteresis of SCSI Receivers 6 10 6 6 Input Current as a Function of Input Voltage 6 10 6 7 Output Current as a Function of Output Voltage 6 11 6 8 External Clock 6 12 6 9 Reset Input 6 13 6 10 In...

Page 12: ...nous Send 6 61 6 38 Target Asynchronous Receive 6 62 6 39 Initiator and Target Synchronous Transfer 6 66 6 40 LSI53C896 329 BGA Bottom View 6 70 6 41 LSI53C896 329 BGA Mechanical Drawing 6 71 B 1 16 K...

Page 13: ...ode of MAD 3 1 Pins 3 23 4 1 PCI Configuration Register Map 4 2 4 2 SCSI Register Map 4 20 4 3 Examples of Synchronous Transfer Periods and Rates for SCSI 1 4 34 4 4 Example Transfer Periods and Rates...

Page 14: ...TS RAM Read 64 Bit 6 19 6 21 Operating Register SCRIPTS RAM Write 32 Bit 6 20 6 22 Operating Register SCRIPTS RAM Write 64 Bit 6 21 6 23 Nonburst Opcode Fetch 32 Bit Address and Data 6 22 6 24 Burst O...

Page 15: ...ers 40 MHz Clock 6 64 6 46 SCSI 2 Fast Transfers 10 0 Mbytes 8 Bit Transfers or 20 0 Mbytes 16 Bit Transfers 50 MHz Clock 6 64 6 47 Ultra SCSI SE Transfers 20 0 Mbytes 8 Bit Transfers or 40 0 Mbytes 1...

Page 16: ...xvi Contents...

Page 17: ...nd allows increased SCSI connectivity and cable length with Low Voltage Differential LVD signaling for SCSI devices The LSI53C896 has a local memory bus for local storage of the device s BIOS ROM in f...

Page 18: ...tem and Figure 1 2 illustrates a typical LSI53C896 board application Figure 1 1 Typical LSI53C896 System Application Fixed Disk Optical Disk Printer Tape and Other Peripherals Fixed Disk Optical Disk...

Page 19: ...Ultra2 SCSI channels in a single package Separate 8 Kbyte internal SCRIPTS RAMs JTAG boundary scanning RAID ready alternative interrupt signaling PC99 Power Management including automatic download of...

Page 20: ...I synchronous transfers as fast as 80 Mbytes s on each channel for a total bandwidth of 160 Mbytes s This advantage is most noticeable in heavily loaded systems or large block size applications such a...

Page 21: ...nals to be actively driven HIGH rather than passively pulled up by terminators Active negation is enabled by setting bit 7 in the SCSI Test Three STEST3 register TolerANT receiver technology improves...

Page 22: ...ve the cost of external differential transceivers Supports a long term performance migration path With a 944 byte FIFO the chip can efficiently burst up to 512 bytes across the PCI bus Two separate SC...

Page 23: ...ts additional arithmetic capability 1 5 2 PCI Performance Complies with the PCI 2 1 specification 64 bit or 32 bit 33 MHz PCI interface Dual Address Cycle DAC can be generated for all SCRIPTS True PCI...

Page 24: ...C8XX family SCRIPTS Direct connection to PCI and SCSI SE LVD and HVD needs external transceivers Development tools and sample SCSI SCRIPTS available Maskable and pollable interrupts Wide SCSI A or P c...

Page 25: ...input Selectable IRQ pin disable bit Ability to route system clock to SCSI clock Compatible with 3 3 V and 5 V PCI 1 5 6 Reliability 2 kV ESD protection on SCSI signals Protection against bus reflecti...

Page 26: ...0 Introduction 1 5 7 Testability All SCSI signals accessible through programmed I O SCSI loopback diagnostics SCSI bus signal continuity checking Support for single step mode operation JTAG boundary s...

Page 27: ...iption Section 2 2 SCSI Functional Description Section 2 3 Parallel ROM Interface Section 2 4 Serial EEPROM Interface Section 2 5 Power Management The LSI53C896 is composed of the following modules 64...

Page 28: ...essor 944 Byte DMA FIFO SCSI FIFO and SCSI Control Block Universal TolerANT Drivers and Receivers 64 Bit PCI Interface PCI Configuration Registers 2 sets Wide Ultra2 SCSI Controller Serial EEPROM Cont...

Page 29: ...der address bits AD 7 0 are used to select a specific 8 bit register Since the LSI53C896 is a PCI multifunction device bits AD 10 8 decode either SCSI Function A Configuration register AD 10 8 0b000 o...

Page 30: ...memory area this device occupies Each SCSI function uses a 8 Kbyte SCRIPTS RAM memory space Base Address Register Two SCRIPTS RAM determines the 8 Kbyte memory area the SCRIPTS RAM occupies 2 1 2 PCI...

Page 31: ...Supported as Master Supported as Slave 0000 Interrupt Acknowledge No No 0001 Special Cycle No No 0010 I O Read Yes Yes 0011 I O Write Yes Yes 0100 Reserved N A N A 0101 Reserved N A N A 0110 Memory R...

Page 32: ...ce The target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects 2 1 2 7 Memory Write Command The Memory Write command writes data to an...

Page 33: ...fetch more than one cache line before disconnecting The LSI53C896 supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple mode is...

Page 34: ...he master intends to fetch a complete cache line This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance adva...

Page 35: ...single PCI transaction unless interrupted by the target This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space The LSI53C896 enables Memor...

Page 36: ...urst size after alignment and issues bursts of this size The burst size is in effect throttled down toward the end of a long Memory Move or Block Move transfer until only the cache line size burst siz...

Page 37: ...the PCI bus 2 1 4 PCI Cache Mode The LSI53C896 supports the PCI specification for an 8 bit Cache Line Size register located in the PCI configuration space The Cache Line Size register provides the ab...

Page 38: ...emory Read or Memory Write will be issued and no cache write alignment will be done 2 1 4 2 Issuing Cache Commands In order to issue each type of PCI cache command the corresponding enable bit must be...

Page 39: ...into the PCI configuration register a Memory Read Multiple command is issued If a transfer will not cross a Dword or cache boundary or if cache mode is not enabled a Memory Read command is issued 2 1...

Page 40: ...ctional Description Table 2 2 PCI Cache Mode Alignment Host Memory A 0x00 B 0x04 0x08 C 0x0C D 0x10 0x14 0x18 0x1C E 0x20 0x24 0x28 0x2C F 0x30 0x34 0x38 0x3C G 0x40 0x44 0x48 0x4C H 0x50 0x54 0x58 0x...

Page 41: ...ory Write and Invalidate Read Example 1 Burst 4 Dwords Cache Line Size 4 Dwords A to B MRL 6 bytes A to C MRL 13 bytes A to D MRL 15 bytes MR 2 bytes C to D MRM 5 bytes C to E MRM 15 bytes MRM 6 bytes...

Page 42: ...es A to D MRM 17 bytes C to D MRM 5 bytes C to E MRM 21 bytes D to F MRM 31 bytes MR 1 byte A to H MRM 31 bytes MRM 32 bytes MRM 18 bytes A to G MRM 31 bytes MRM 32 bytes MR 3 bytes A to B MRL 6 bytes...

Page 43: ...6 bytes A to C MW 13 bytes A to D MW 17 bytes C to D MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 16 bytes MWI 16 bytes MWI 16...

Page 44: ...Dwords A to B MW 6 bytes A to C MW 13 bytes A to D MW 17 bytes C to D MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 32 bytes MWI...

Page 45: ...d Invalidate commands are issued The LSI53C896 is little endian only 2 2 SCSI Functional Description The LSI53C896 provides two Ultra2 SCSI controllers on a single chip Each Ultra2 SCSI controller pro...

Page 46: ...is a special high speed processor optimized for SCSI protocol 2 2 1 SCRIPTS Processor The SCSI SCRIPTS processor allows both DMA and SCSI commands to be fetched from host memory or internal SCRIPTS RA...

Page 47: ...designed for SCRIPTS program storage but is not limited to this type of information When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM these fetches remain...

Page 48: ...fault to zero meaning the LSI53C896 will power up in a state where only Single Address Cycles SACs will be generated When any of the selector registers are written to a nonzero value DACs will be gene...

Page 49: ...bilities to guarantee Ultra2 SCSI transfer rates For additional information on Ultra2 SCSI refer to the SPI 2 working document which is available from the SCSI BBS referenced at the beginning of this...

Page 50: ...fetches 8 Dwords of instruction The prefetch logic automatically determines the maximum burst size that it can perform based on the burst length as determined by the values in the DMA Mode DMODE regis...

Page 51: ...execute is not the sequential next instruction in the prefetch unit When the Prefetch Flush bit DMA Control DCNTL register bit 6 is set The unit flushes whenever this bit is set The bit is self clear...

Page 52: ...ption which is explained in this section This device accepts all required boundary scan instructions including the optional CLAMP HIGH Z and IDCODE instructions The LSI53C896 uses an 8 bit instruction...

Page 53: ...sors Programming Guide 2 2 11 Parity Options The LSI53C896 implements a flexible parity scheme that allows control of the parity sense allows parity checking to be turned on or off and has the ability...

Page 54: ...rity Error SCSI Interrupt Status Zero SIST0 Bit 0 This status bit is set whenever the LSI53C896 detects a parity error on the SCSI bus Status of SCSI Parity Signal SCSI Status Zero SSTAT0 Bit 0 This s...

Page 55: ...1 1 Checks for odd parity on SCSI data received Parity is generated when sending SCSI data Asserts even parity when sending SCSI data Table 2 5 SCSI Parity Errors and Interrupts DHP1 1 DHP Disable Hal...

Page 56: ...in the Chip Test Five CTEST5 register PCI Interface DMA FIFO 64 Bits x 118 SODL Register SCSI Interface X S PCI Interface DMA FIFO 64 Bits x 118 SIDL Register SCSI Interface G X PCI Interface DMA FIFO...

Page 57: ...12 1 Data Paths The data path through the LSI53C896 is dependent on whether data is being moved into or out of the chip and whether SCSI data is being transferred asynchronously or synchronously Figu...

Page 58: ...ract the 10 least significant bits of the DMA Byte Counter DBC register from the 10 bit value of the DMA FIFO Byte Offset Counter which consists of bits 1 0 in the Chip Test Five CTEST5 register and b...

Page 59: ...consists of bits 1 0 in the Chip Test Five CTEST5 register and bits 7 0 of the DMA FIFO DFIFO register AND the result with 0x3FF for a byte count between zero and 944 Step 2 Read bit 5 in the SCSI Sta...

Page 60: ...t significant byte is full Step 3 If any wide transfers have been performed using the Chained Move instruction read the Wide SCSI Receive bit SCSI Control Two SCNTL2 bit 0 to determine whether a byte...

Page 61: ...ctivity and a longer SCSI cable the LSI53C896 features LVDlink technology the LSI Logic implementation of LVD SCSI LVDlink transceivers provide the inherent reliability of differential SCSI and a long...

Page 62: ...SDP0 lines is 680 when the Active Negation portion of LSI Logic TolerANT technology is not enabled When TolerANT technology is enabled the recommended resistor value on the SREQ SACK SD 7 0 and SDP0 s...

Page 63: ...L BSY RST REQ BSY RST ACK MSG C_D I_O ATN VDD 1 5 K DIFFSENS Schottky Diode DIFFSENS pin 21 SEL SCSI Bus SEL BSY BSY RST 42 RST REQ REQ ACK ACK MSG MSG C D C D I O I O ATN ATN 1B 1B 2B 2B 3B 3B 4B 4B...

Page 64: ...he SSEL SBSY and SRST SCSI signals to be asserted on the SCSI bus The differential pairs on the SCSI bus are reversed when connected to the SN75976A due to the active low nature of the SCSI bus 8 Bit...

Page 65: ...7 11 12 13 14 15 16 17 Line1 Line1 Line2 Line2 Line3 Line3 Line4 Line4 Line5 Line5 DISCNCT Line9 Line9 Line8 Line8 Line7 Line7 Line6 Line6 SE LVD HVD DIFFSENS DIFF B 32 31 30 29 25 24 23 22 33 34 35 2...

Page 66: ...is enabled the LSI53C896 cannot be reselected as an initiator There are also status and interrupt bits in the SCSI Interrupt Status Zero SIST0 and SCSI Interrupt Enable Zero SIEN0 registers respectiv...

Page 67: ...divider controls the rate at which data can be received This rate must not exceed 160 MHz The receive rate of SCLK Clock Quadrupler QCLK SCF Divider CCF Divider Synchronous Divider Asynchronous SCSI...

Page 68: ...us transfer specifications It allows synchronous transfer periods to be negotiated down as low as 25 ns which is half the 50 ns period allowed under Ultra SCSI This will allow a maximum transfer rate...

Page 69: ...other system tasks The preferred method of detecting interrupts in most systems is hardware interrupts In this case the LSI53C896 asserts the Interrupt Request INTA or INTB line that interrupts the m...

Page 70: ...Interrupt Status Zero ISTAT0 register is set then a DMA type interrupt has occurred and the DMA Status DSTAT register should be read SCSI type and DMA type interrupts may occur simultaneously so in s...

Page 71: ...DMA Interrupt Enable DIEN register is the interrupt enable register for DMA interrupts in DMA Status DSTAT DMA Control DCNTL When bit 1 in this register is set the INTA or INTB pin is not asserted whe...

Page 72: ...CMP set when the LSI53C896 is selected or reselected SEL or RSL set when the initiator asserts ATN target mode SATN active or when the General Purpose or Handshake to Handshake timers expire These in...

Page 73: ...ing hardware interrupts then masking a fatal interrupt makes no difference since the SIP and DIP bits in the Interrupt Status Zero ISTAT0 inform the system of interrupts not the INTA or INTB pin Maski...

Page 74: ...DMA interrupts do not attempt to flush the FIFOs before generating the interrupt It is important to set either the Clear DMA FIFO CLF and Clear SCSI FIFO CSF bits if a DMA interrupt occurs and the DMA...

Page 75: ...CSI interrupt condition and get the SCSI interrupt status The bits in the SIST0 and SIST1 tell which SCSI interrupts occurred and determine what action is required to service the interrupts 4 If only...

Page 76: ...SI controllers that are to be serviced by the RAID upgrade card An upgrade slot is one that is connected to the interrupt routing logic for mainboard SCSI device s When a PCI RAID upgrade board is ins...

Page 77: ...d to a RAID adapter however a mechanism must be implemented to prevent the SCSI BIOS and operating system driver from trying to access the SCSI core The mainboard designer has several options to choos...

Page 78: ...rating systems make PCI BIOS calls This approach requires modifications to the system BIOS and assumes the operating system uses PCI BIOS calls when searching for PCI devices 2 2 18 Chained Block Move...

Page 79: ...r the target and the controller detects a partial transfer at the end of a chained Block Move SCRIPTS instruction this flag is not set if a normal Block Move instruction is used Under this condition t...

Page 80: ...e uses the WSR bit to determine what behavior must occur at the start of the next data receive transfer The bit is automatically cleared at the start of the next data receive transfer The bit can alte...

Page 81: ...er occurs similar to that of the regular Block Move instruction Whether the WSR bit is set or cleared when a normal block move instruction is executed the contents of the SWIDE register are ignored an...

Page 82: ...ystem requirements include the LSI53C896 two or three external 8 bit address holding registers HCT273 or HCT374 and the appropriate memory device The 4 7 k pull up resistors on the MAD bus require HC...

Page 83: ...ll downs on all of the MAD bus signals The LSI53C896 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI configuration spa...

Page 84: ...s pulled down internally GPIO0 is the serial data signal SDA and GPIO1 is the serial clock signal SCL Certain data in the serial EEPROM is automatically loaded into chip registers at power up or hard...

Page 85: ...mat Byte Name Description 0xFB SVID 0 Subsystem Vendor ID LSB This byte is loaded into the least significant byte of the Subsystem Vendor ID register in the appropriate PCI configuration space at chip...

Page 86: ...tion As the device transitions from one power level to a lower one the attributes that occur from the higher power state level are carried over into the lower power state level For example D1 disables...

Page 87: ...power state D2 to power state D1 or D0 the previous values of the PCI Command register are restored Also any pending interrupts before the function entered power state D2 are asserted 2 5 4 Power Sta...

Page 88: ...2 62 Functional Description...

Page 89: ...3 4 Flash ROM and Memory Interface Signals Section 3 5 Test Interface Signals Section 3 6 Power and Ground Signals Section 3 7 MAD Bus Programming The PCI Interface signals are divided into the follo...

Page 90: ...MAD 7 0 SCLK A_SD 15 0 A_SDP 1 0 A_SC_D A_SI_O A_SMSG A_SREQ A_SACK A_SACK2 A_SBSY A_SATN A_SRST A_SSEL B_SDP 1 0 B_SC_D B_SI_O B_SMSG B_SREQ B_SACK B_SACK2 B_SBSY B_SATN B_SRST B_SSEL B_SD 15 0 TEST...

Page 91: ...ly signal O Output a standard output driver typically a Totem Pole Output I O Input and output bidirectional T S 3 state a bidirectional 3 state input output signal S T S Sustained 3 state an active L...

Page 92: ...INTA ALT_INTB 25 A Pull up enabled when the AND tree mode is enabled by driving TEST_RST LOW or when the IRQ mode bit bit 3 of DCNTL 0X3B is cleared 1 INT_DIR TCK TDI TEST_RST TMS 25 A Pulled up inter...

Page 93: ...e Strength Description CLK H3 I N A Clock provides timing for all transactions on the PCI bus and is an input to every PCI device All other PCI signals are sampled on the rising edge of CLK and other...

Page 94: ...he address during the second clock of the transaction During subsequent clocks AD 63 0 contain data PCI supports both read and write bursts AD 7 0 define the least significant byte and AD 63 56 define...

Page 95: ...icate that a bus transaction is beginning While FRAME is deasserted either the transaction is in the final data phase or the bus is idle TRDY P3 S T S 16 mA PCI Target Ready indicates the target agent...

Page 96: ...n selected IDSEL L3 I N A Initialization Device Select is used as a chip select in place of the upper 24 address lines during configuration read and write transactions Table 3 4 Interface Control Sign...

Page 97: ...tive by an agent that detects a data parity error PERR can be used by any agent to signal data corruption However on detection of a PERR pulse the central resource may generate a nonmaskable interrupt...

Page 98: ...interrupt pin is disabled if INT_DIR is driven LOW ALT_INTA F1 O 16 mA PCI Alt Interrupt Function A When asserted LOW it indicates an interrupting condition has occurred in SCSI Function A The output...

Page 99: ...in Control GPCNTL register is set Or it can be used to indicate that the next bus request will be an opcode fetch if bit 6 in the GPCNTL register is set A_GPIO1_ MASTER Y16 I O 8 mA SCSI Function A Ge...

Page 100: ...ntrol GPCNTL register is set Or it can be used to indicate that the next bus request will be an opcode fetch if bit 6 in the GPCNTL register is set B_GPIO1_ MASTER AC15 I O 8 mA SCSI Function B Genera...

Page 101: ...als group 3 3 1 SCSI Function A Signals This section describes the signals for the SCSI Function A Signals group It is divided into two tables SCSI Function A Signals and SCSI Function A_SCTRL Signals...

Page 102: ...SI SCSI Function A Data and Parity LVD Mode Positive half of LVDlink pair for SCSI data lines A_SD 15 0 are the 16 bit data bus and A_SDP 1 0 are the SCSI data parity lines SE Mode A_SD 15 0 and A_SDP...

Page 103: ...nput output SCSI phase line message Data handshake line from target device Data handshake line from target device Duplicate of A_SREQ enabled by pulling MAD 5 HIGH at reset Data handshake signal from...

Page 104: ...ative half of LVDlink pair for SCSI data and parity lines B_SD 15 0 are the 16 bit SCSI data bus and B_SDP 1 0 are the SCSI data parity lines SE Mode B_SD 15 0 are the 16 bit SCSI data bus and B_SDP 1...

Page 105: ...sent on this pin the SCSI Function B will operate in the LVD mode SE Mode When this pin is driven LOW below 0 5 V indicating SE bus operation the SCSI Function B will operate in the SE mode HVD Mode W...

Page 106: ...phase line message Data handshake line from target device Data handshake line from target device Duplicate of B_SREQ enabled by pulling MAD 6 HIGH at reset Data handshake signal from the initiator de...

Page 107: ...ch in the least significant address byte bits 7 0 of an external EPROM or flash memory Since the LSI53C896 moves addresses eight bits at a time this pin connects to the clock of an external bank of fl...

Page 108: ...d as an output enable signal to an external EPROM or flash memory during read operations It is also used to test the connectivity of the LSI53C896 signals in the AND tree test mode The MOE _TESTOUT pi...

Page 109: ...upler and diffsense logic VSS A B20 G N A Ground for analog cells clock quadrupler and diffsense logic VDD Bias M22 P N A Power for LVD bias current VDD Bias2 A11 P N A Power for LVD bias current RBIA...

Page 110: ...be pulled LOW by the internal pull down current sink the duplicate SCSI REQ and ACK signals for channel B are disabled When pulled HIGH by an external resistor the duplicate SCSI REQ and ACK signals...

Page 111: ...icates a pull up resistor attached MAD 0 slow ROM When pulled up it enables two extra cycles of data access time to allow use of slower memory devices Note All MAD pins have internal pull down resisto...

Page 112: ...3 24 Signal Descriptions...

Page 113: ...the default register values which are enabled after the chip is powered on or reset This chapter contains the following sections Section 4 1 PCI Configuration Registers Section 4 2 SCSI Registers Sec...

Page 114: ...egister Map 31 16 15 0 Device ID Vendor ID 0x00 Status Command 0x04 Class Code Revision ID Rev ID 0x08 Not Supported Header Type Latency Timer Cache Line Size 0x0C Base Address Register Zero I O 0x10...

Page 115: ...xcept configuration accesses R Reserved 15 9 SE SERR Enable 8 This bit enables the SERR driver SERR is disabled when this bit is cleared The default value of this bit is zero This bit and bit 6 must b...

Page 116: ...master in order to fetch SCRIPTS instructions and transfer data EMS Enable Memory Space 1 This bit controls the ability of the LSI53C896 to respond to Memory space accesses A value of zero disables th...

Page 117: ...arity error even if data parity error handling is disabled SSE Signaled System Error 14 This bit is set whenever the device asserts the SERR signal RMA Received Master Abort from Master 13 A master de...

Page 118: ...t setting this bit acted as the bus master for the operation in which the error occurred and The Parity Error Response bit in the Command register is set R Reserved 7 5 NC New Capabilities 4 This bit...

Page 119: ...ize in units of 32 bit words The value in this register is used by the device to determine whether to use Write and Invalidate or Write commands for performing write cycles and whether to use Read Rea...

Page 120: ...ion to calculate an optimum latency value for the SCSI functions of the LSI53C896 Latency 2 Burst Size x typical wait states 1 Values greater than optimum are also acceptable Register 0x0E Header Type...

Page 121: ...to the PCI 2 1 specification Registers 0x14 0x1B Base Address Register One MEMORY Read Write BAR1 Base Address Register One 63 0 This base address register maps SCSI operating registers into memory s...

Page 122: ...004 The LSI53C896 requires 8192 bytes of address space for this base register This register has bits 12 0 hardwired to 0b0000000000100 For detailed information on the operation of this register refer...

Page 123: ...is enabled MAD 7 LOW this register is automatically loaded at power up from the external serial EEPROM and will contain the value downloaded from the serial EEPROM or a value of 0x0000 if the download...

Page 124: ...downloaded from the serial EEPROM or a value of 0x0000 if the download fails If the external serial EEPROM is disabled MAD 7 pulled HIGH the register returns a value of 0x1000 The 16 bit value that sh...

Page 125: ...host system detects the size of the external memory by first writing the Expansion ROM Base Address register with all ones and then reading back the register The SCSI functions of the LSI53C896 respo...

Page 126: ...system architecture Register 0x3D Interrupt Pin Read Only IP Interrupt Pin 7 0 This register is unique to each SCSI function It tells which interrupt pin the device uses Its value is set to 0x01 for t...

Page 127: ...ters is in units of 0 25 microseconds The LSI53C896 sets this register to 0x11 Register 0x3F Max_Lat Read Only ML Max_Lat 7 0 This register is used to specify the desired settings for latency timer va...

Page 128: ...nction s capabilities list The LSI53C896 has these bits set to zero indicating no further extended capabilities registers exist Registers 0x42 0x43 Power Management Capabilities PMC Read Only PMES PME...

Page 129: ...o use it R Reserved 4 PMEC PME Clock 3 Bit 3 is cleared because the LSI53C896 does not provide a PME pin VER 2 0 Version 2 0 These three bits are set to 0b010 to indicate that the LSI53C896 complies w...

Page 130: ...1 0 are used to determine the current power state of the LSI53C896 They are used to place the LSI53C896 in a new power state Power states are defined as See the Section 2 5 Power Management for descr...

Page 131: ...nction has the identical register set The address map of the SCSI registers is shown in Table 4 2 Note The only registers that the host CPU can access while the LSI53C896 is executing SCRIPTS are the...

Page 132: ...D 0x28 DSP 0x2C DSPS 0x30 SCRATCH A 0x34 DCNTL SBR DIEN DMODE 0x38 ADDER 0x3C SIST1 SIST0 SIEN1 SIEN0 0x40 GPCNTL CTYPE SWIDE SLPAR 0x44 RESPID1 RESPID0 STIME1 STIME0 0x48 STEST3 STEST2 STEST1 STEST0...

Page 133: ...us Zero SSTAT0 register 3 After an arbitration delay the CPU should read the SCSI Bus Data Lines SBDL register to check if a higher priority SCSI ID is present If no higher priority ID bit is set and...

Page 134: ...SCSI Destination ID SDID register and the LSI53C896 s ID stored in the SCSI Chip ID SCID register 6 After a selection is complete the Function Complete bit is set in the SCSI Interrupt Status Zero SI...

Page 135: ...T0 register is set and an interrupt may be generated If the LSI53C896 SCSI function is operating in the initiator mode and a parity error is detected assertion of SATN is optional but the transfer con...

Page 136: ...me Setting this bit only affects SCSI send operations ADB Assert SCSI Data Bus 6 When this bit is set the LSI53C896 SCSI function drives the contents of the SCSI Output Data Latch SODL register onto t...

Page 137: ...when it has responded to a bus initiated selection or reselection This bit is also set after the chip wins simple arbitration when operating in low level mode When this bit is cleared the LSI53C896 SC...

Page 138: ...rt an immediate arbitration sequence First set the Abort bit in the Interrupt Status Zero ISTAT0 register Then one of two things eventually happens The Won Arbitration bit SCSI Status Zero SSTAT0 bit...

Page 139: ...d or successfully selects another SCSI device The SDU bit should be cleared with a register write Move 0x00 To SCSI Control Two SCNTL2 before the SCSI core expects a disconnect to occur normally prior...

Page 140: ...inal Parity SLPAR register If this bit is set the high byte of the SLPAR word is present in the SLPAR register WSS Wide SCSI Send 3 When read this bit returns the value of the Wide SCSI Send WSS flag...

Page 141: ...r nonchained block move command and temporarily stored the high order byte in the SCSI Wide Residue SWIDE register rather than passing the byte out the DMA channel The hardware uses the WSR status fla...

Page 142: ...the SCF bits are used to calculate synchronous transfer periods See the table under the description of bits 7 5 of the SXFER register for the valid combinations EWS Enable Wide SCSI 3 When this bit i...

Page 143: ...ically reconfigure itself to the initiator mode as a result of being reselected SRE Enable Response to Selection 5 When this bit is set the LSI53C896 SCSI function is able to respond to bus initiated...

Page 144: ...The priority of the 16 possible IDs in descending order is Register 0x05 SCSI Transfer SXFER Read Write Note When using Table Indirect I O commands bits 7 0 of this register are loaded from the I O da...

Page 145: ...found as follows SXFERP Period SSCP ExtCC Period 1 Frequency 1 10 Mbytes s 100 ns SSCP 1 SSCF 1 40 MHz 25 ns This SCSI synchronous core clock is determined in SCNTL3 bits 6 4 ExtCC 1 if SCNTL1 bit 7 i...

Page 146: ...SI 2 Ultra and Ultra 2 Table 4 3 Examples of Synchronous Transfer Periods and Rates for SCSI 1 CLK MHz SCSI CLK SCNTL3 Bits 6 4 XFERP Synch Transfer Period ns Synch Transfer Rate Mbytes 66 67 3 4 180...

Page 147: ...I53C896 SCSI function These bits determine the LSI53C896 SCSI function s method of transfer for Data In and Data Out phases only All other information transfers occur asynchronously Table 4 4 Example...

Page 148: ...1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 0 0 1 1 1 7 0 1 0 0 0 8 0 1 0 0 1 9 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1 13 0 1 1 1 0 14 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 1 0 0 1 1 19 1...

Page 149: ...n descending order is Register 0x07 General Purpose GPREG Read Write A write to this register will cause the data written to be output to the appropriate GPIO pin if it is set to output mode in that f...

Page 150: ...in the initiator mode this register contains the first byte received in the Message In Status and Data In phases When a Block Move instruction is executed for a particular phase the first byte receiv...

Page 151: ...ad Write REQ Assert SCSI REQ Signal 7 ACK Assert SCSI ACK Signal 6 BSY Assert SCSI BSY Signal 5 SEL Assert SCSI SEL Signal 4 ATN Assert SCSI ATN Signal 3 MSG Assert SCSI MSG Signal 2 C_D Assert SCSI C...

Page 152: ...ID SSID register immediately after the LSI53C896 SCSI function is selected or reselected returns the binary encoded SCSI ID of the device that performed the operation These bits are invalid for targe...

Page 153: ...er in case additional interrupts are pending the LSI53C896 SCSI functions stack interrupts The DIP bit in the Interrupt Status Zero ISTAT0 register is also cleared It is possible to mask DMA interrupt...

Page 154: ...ter SSI Single Step Interrupt 3 If the Single Step Mode bit in the DMA Control DCNTL register is set this bit is set and an interrupt generated after successful execution of each SCRIPTS instruction S...

Page 155: ...chip is in target mode A Load Store instruction is issued with the memory address mapped to the operating registers of the chip not including ROM or RAM A Load Store instruction is issued when the reg...

Page 156: ...ing data synchronously It is not readable or writable by the user It is possible to use this bit to determine how many bytes reside in the chip when an error occurs OLF SODL Least Significant Byte Ful...

Page 157: ...SCSI Control Zero SCNTL0 register must be full arbitration and selection to set this bit RST SCSI RST Signal 1 This bit reports the current status of the SCSI RST signal and the RST signal bit 3 in th...

Page 158: ...0 1 1 3 0 0 1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 0 0 1 1 1 7 0 1 0 0 0 8 0 1 0 0 1 9 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1 13 0 1 1 1 0 14 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 1...

Page 159: ...d Only ILF SIDL Most Significant Byte Full 7 This bit is set when the most significant byte in the SCSI Input Data Latch SIDL contains data Data is transferred from the SCSI bus to the SCSI Input Data...

Page 160: ...omplete description of this field see the definition for SSTAT1 bits 7 4 SPL1 Latched SCSI parity for SD 15 8 3 This active HIGH bit reflects the SCSI odd parity signal corresponding to the data latch...

Page 161: ...ster 0x14 Interrupt Status Zero ISTAT0 Read Write This is the only register that is accessible by the host CPU while a LSI53C896 SCSI function is executing SCRIPTS without interfering in the operation...

Page 162: ...s and all SCSI signals are deasserted Setting this bit does not assert the SCSI RST signal This reset does not clear the ID Mode bit or any of the PCI configuration registers This bit is not self clea...

Page 163: ...selection or reselection It is also set after the SCSI function wins arbitration when operating in low level mode When this bit is cleared the LSI53C896 SCSI function is not connected to the SCSI bus...

Page 164: ...ed The handshake to handshake timer is expired The general purpose timer is expired To determine exactly which condition s caused the interrupt read the SCSI Interrupt Status Zero SIST0 and SCSI Inter...

Page 165: ...is cleared the SCRIPTS engine is not active This bit is read only and writes will have no effect on the value of this bit SI SYNC_IRQD 0 Setting this bit disables the INTA pin for Function A and the...

Page 166: ...er as a read only and the other as a write only will prevent this type of conflict Register 0x17 Mailbox One MBOX1 Read Write MBOX1 Mailbox One 7 0 These are general purpose bits that may be read or w...

Page 167: ...he status of bytes at the bottom of the FIFO if all FMT bits are set the DMA FIFO is empty Register 0x19 Chip Test One CTEST1 Read Only FFL Byte Full in DMA FIFO 7 0 These status bits identify the top...

Page 168: ...O Enable Status bit This read only bit indicates if the chip is currently enabled as I O space CM Configured as Memory 4 This bit is defined as the configuration memory enable status bit This read on...

Page 169: ...ormal operation Note Bit 3 is the only writable bit in this register All other bits are read only When modifying this register all other bits must be written to zero Do not execute a Read Modify Write...

Page 170: ...red by the LSI53C896 SCSI function Note Polling of FIFO flags is allowed during flush operations CLF Clear DMA FIFO 2 When this bit is set all data pointers for the DMA FIFO are cleared Any data in th...

Page 171: ...r DSP register when a Return instruction is executed This address points to the next instruction to execute Do not write to this register while the LSI53C896 SCSI function is executing SCRIPTS During...

Page 172: ...ip Test Five CTEST5 is set Step 1 Subtract the ten least significant bits of the DMA Byte Counter DBC register from the 10 bit value of the DFBOC which is made up of the Chip Test Five CTEST5 register...

Page 173: ...y Memory to Memory Move operations When this bit is set register accesses to the Temporary TEMP and Data Structure Address DSA registers are directed to the shadow copies STEMP Shadow TEMP and SDSA Sh...

Page 174: ...e FBL3 bit is set then FBL2 through FBL0 determine which of eight byte lanes can be read or written When cleared the byte lane read or written is determined by the current contents of the DMA Next Add...

Page 175: ...bytes deep When set the DMA FIFO size increases to 944 bytes Using an 112 byte FIFO allows software written for other LSI53C8XX family chips to properly calculate the number of bytes residing in the...

Page 176: ...7 0 Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four CTEST4 register Reading this register unloads data from the a...

Page 177: ...ferred The maximum number of bytes that can be transferred in any one Block Move command is 16 777 215 bytes The maximum value that can be loaded into the DMA Byte Counter DBC register is 0xFFFFFF If...

Page 178: ...e general purpose address pointer At the start of some SCRIPTS operations its value is copied from the DMA SCRIPTS Pointer Save DSPS register Its value may not be valid except in certain abort conditi...

Page 179: ...tep interrupt occurs to fetch and execute the next SCRIPTS command When writing this register eight bits at a time writing the upper eight bits begins execution of SCSI SCRIPTS The default value of th...

Page 180: ...read Bits 9 0 of SCRATCH A will always return zero in this mode Writes to the SCRATCHA register are unaffected Clearing the PCI Configuration Info Enable bit causes the SCRATCH A register to return t...

Page 181: ...lts in burst lengths The big FIFO mode can be activated by setting bit 5 of the Chip Test Five CTEST5 register SIOM Source I O Memory Enable 5 This bit is defined as an I O Memory Enable bit for the s...

Page 182: ...ch Enable 1 Setting this bit causes the LSI53C896 SCSI function to fetch instructions in burst mode Specifically the chip bursts in the first two Dwords of all instructions using a single bus ownershi...

Page 183: ...the appropriate mask bit Masking an interrupt prevents INTA for Function A or INTB for Function B from being asserted for the corresponding interrupt but the status bit is still set in the DMA Status...

Page 184: ...read write and memory moves into this register alter its contents The default value of this register is zero This register is called the DMA Watchdog Timer on previous LSI53C8XX family products Regist...

Page 185: ...efetch unit will fetch instructions in two bursts of 4 Dwords If the burst threshold is set to 16 Dwords or greater the prefetch unit will fetch instructions in one burst of 8 Dwords Burst thresholds...

Page 186: ...it 4 in the DMA Control DCNTL register is set When the LSI53C896 SCSI function is executing SCRIPTS in manual start mode the Start DMA bit must be set to start instruction fetches but need not be set...

Page 187: ...ions that initialize the SCSI First Byte Received SFBR register When the COM bit is set the ID is stored only in the SCSI Selector ID SSID register protecting the SCSI First Byte Received SFBR from be...

Page 188: ...r This expected phase is automatically written by SCSI SCRIPTS In the target mode this bit is set when the initiator asserts SATN See the Disable Halt on Parity Error or SATN Condition bit in the SCSI...

Page 189: ...isconnect 2 This condition only occurs in the initiator mode It happens when the target to which the LSI53C896 SCSI function is connected disconnects from the SCSI bus unexpectedly See the SCSI Discon...

Page 190: ...changes modes IRQ does not assert and the SIP bit in the Interrupt Status Zero ISTAT0 register is not set However bit 4 in the SCSI Interrupt Status One SIST1 register is set Setting this bit allows...

Page 191: ...g the LSI53C896 SCSI functions stack interrupts SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero SIEN0 register When performing consecutive 8 bit reads of the D...

Page 192: ...ID One RESPID1 registers must hold the chip s ID for the LSI53C896 SCSI function to respond to reselection attempts SGE SCSI Gross Error 3 This bit is set when the LSI53C896 SCSI function encounters a...

Page 193: ...t may occur before at the same time or stacked after the STO interrupt since this is not considered an expected disconnect RST SCSI RST Received 1 This bit is set when the LSI53C896 SCSI function dete...

Page 194: ...ng to select or reselect does not respond within the programmed time out period See the description of the SCSI Timer Zero STIME0 register bits 3 0 for more information on the time out timer GEN Gener...

Page 195: ...bus all signals are shown active HIGH A one in any bit position of the final SLPAR value would indicate a transmission error The SLPAR register is also used to generate the check bytes for SCSI send o...

Page 196: ...e of the current longitudinal parity value and the low byte of the SCSI bus is XORed with the low byte of the current longitudinal parity value In this mode the 16 bit longitudinal parity value is acc...

Page 197: ...identify the device R Reserved 3 0 Register 0x47 General Purpose Pin Control GPCNTL Read Write This register is used to determine if the pins controlled by the General Purpose GPREG are inputs or out...

Page 198: ...tput and GPIO 3 2 power up as general purpose inputs GPIO GPIO Enable 1 0 These bits power up set causing the GPIO1 and GPIO0 pins to become inputs Clearing these bits causes GPIO 1 0 to become output...

Page 199: ...to Chapter 2 Functional Description HTH 7 4 SEL 3 0 GEN 3 0 1 Minimum Time Out 40 or 160 MHz 2 0000 Disabled 0001 125 s 0010 250 s 0011 500 s 0100 1 ms 0101 2 ms 0110 4 ms 0111 8 ms 1000 16 ms 1001 3...

Page 200: ...mer to begin testing for SCSI REQ and ACK activity as soon as SBSY is asserted regardless of the agents participating in the transfer GENSF General Purpose Timer Scale Factor 5 Setting this bit causes...

Page 201: ...SCSI Timer Zero STIME0 bits 3 0 for the available time out periods HTH 7 4 SEL 3 0 GEN 3 0 1 Minimum Time out 50 MHz Clock 2 HTHSF 0 GENSF 0 HTHSF 1 GENSF 1 0000 Disabled Disabled 0001 100 s 1 6 ms 0...

Page 202: ...NSF 0 HTHSF 1 GENSF 1 0000 Disabled Disabled 0001 125 s 2 ms 0010 250 s 4 ms 0011 500 s 8 ms 0100 1 s 16 ms 0101 2 ms 32 ms 0110 4 ms 64 ms 0111 8 ms 128 ms 1000 16 ms 256 ms 1001 32 ms 512 ms 1010 64...

Page 203: ...use more than one bit can be set in the RESPID1 and RESPID0 registers However the chip can arbitrate with only one ID value in the SCSI Chip ID SCID register Register 0x4B Response ID One RESPID1 Read...

Page 204: ...se ID Zero RESPID0 and Response ID One RESPID1 registers to allow response to multiple IDs on the bus SLT Selection Response Logic Test 3 This bit is set when the LSI53C896 SCSI function is ready to b...

Page 205: ...SI is functioning as an initiator then the target has sent the offset number of requests Register 0x4D SCSI Test One STEST1 Read Write SCLK SCSI Clock 7 When set this bit disables the external SCLK SC...

Page 206: ...four different interrupt routing modes These modes are described in the following table Each SCSI core within the chip can be configured independently Mode 0 is the default mode and is compatible wit...

Page 207: ...t this bit This bit automatically clears itself after resetting the synchronous offset DIF HVD or SE LVD 5 Setting this bit allows the LSI53C896 SCSI function to interface to external HVD transceivers...

Page 208: ...ing edge of the SREQ and SACK signals Note Never set this bit during fast SCSI greater than 5 Mbytes transfers per second operations because a valid assertion could be treated as a glitch LOW SCSI Low...

Page 209: ...T Active negation should be enabled to improve setup and deassertion times Active negation is disabled after reset or when this bit is cleared For more information on LSI Logic TolerANT technology see...

Page 210: ...reselection assuming parity checking has been enabled If an 8 bit SCSI device attempts to select the LSI53C896 while this bit is set the LSI53C896 will ignore the selection attempt This is because th...

Page 211: ...read from this register Data can be written to the SCSI Output Data Latch SODL register and then read back into the LSI53C896 by reading this register to allow loopback testing When receiving SCSI dat...

Page 212: ...bit values are defined in the following table LOCK Frequency Lock 5 This bit is used when enabling the SCSI clock quadrupler which allows the LSI53C896 to transfer data at Ultra2 SCSI rates Poll this...

Page 213: ...e ENPMJ Enable Phase Mismatch Jump 7 Upon setting this bit any phase mismatches do not interrupt but force a jump to an alternate location to handle the phase mismatch Prior to actually taking the jum...

Page 214: ...ump On Nondata Phase Mismatches 5 This bit controls whether or not a jump is taken during a nondata phase mismatch i e message in message out status or command When this bit is cleared jumps will only...

Page 215: ...overlapped arbitration will be disabled and PCI REQ will not be asserted during a PCI master cycle being executed by this chip Register 0x57 Chip Control 1 CCNTL1 Read Write ZMOD High Impedance Mode...

Page 216: ...bility This bit will only function if the EN64TIBMV bit is set Index Mode 0 64TIMOD clear table entry format Index Mode 1 64TIMOD set table entry format EN64TIBMV Enable 64 bit Table Indirect BMOV 1 S...

Page 217: ...Control Three SCNTL3 bit 3 and SCSI Test Two STEST2 bit 2 are set and SCSI Bus Data Lines SBDL is read both byte lanes are checked for parity regardless of phase When in a nondata phase this will cau...

Page 218: ...of SCRATCH B will always return zeros in this mode Writes to the SCRATCH B register are unaffected Resetting the PCI Configuration Info Enable bit causes the SCRATCH B register to return to normal op...

Page 219: ...efore they are used All selectors can be read written using the Load Store SCRIPTS instruction Memory to Memory Move Read Write SCRIPTS instruction or CPU with SCRIPTS not running Note Crossing of sel...

Page 220: ...dress Register Two SCRIPTS RAM in bits 31 0 of the MMWS register when read Writes to the MMWS register are unaffected Clearing the PCI Configuration Info Enable bit causes the MMWS register to return...

Page 221: ...F DSA Relative Selector DRS Read Write DRS DSA Relative Selector 31 0 Supplies AD 63 32 during table indirect fetches and Load Store Data Structure Address DSA relative operations Registers 0xB0 0xB3...

Page 222: ...data address upon execution of 64 bit direct BMOVs Registers 0xB8 0xBB DMA Next Address 64 DNAD64 Read Write DNAD64 DMA Next Address 64 31 0 This register holds the current selector being used in a gi...

Page 223: ...e 32 bit address that will be jumped to upon a phase mismatch Depending upon the state of the PMJCTL bit this address will either be used during an outbound data out command message out phase mismatch...

Page 224: ...of this register will also contain the opcode of the BMOV that was executing In the case of a table indirect BMOV instruction the upper byte will contain the upper byte of the table indirect entry tha...

Page 225: ...ed The SWIDE byte must be manually written to memory and this address must be incremented prior to updating any scatter gather entry In the case of a SCSI data receive if there is not a byte in the SW...

Page 226: ...se the ESA will have the address of the table indirect entry and this register will point to the address of the BMOV instruction 31 0 ESA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 227: ...r of bytes sent by one This will also happen in an odd byte count wide receive case Also in the case of a wide send in which there is a chain byte from a previous transfer the count will not reflect t...

Page 228: ...l count bytes as long as the phase mismatch enable ENPMJ in the Chip Control 0 CCNTL0 register is set Unlike the SCSI Byte Count SBC this count will not be cleared on each BMOV instruction but will co...

Page 229: ...us sequences to operate properly Another feature allowed at the low level is loopback testing In loopback mode the SCSI core can be directed to talk to the DMA core to test internal data paths all the...

Page 230: ...g to the low level mode for error recovery is not required The following types of SCRIPTS instructions are implemented in the LSI53C896 Block Move used to move data between the SCSI bus and memory I O...

Page 231: ...e in the DMA FIFO to transfer a programmable size block of data For a SCSI receive operation it waits until enough data is collected in the DMA FIFO for transfer to memory At this point the LSI53C896...

Page 232: ...memory or I O space When data is moved onto the SCSI bus SIOM controls whether that data comes from I O or memory space When data is moved off of the SCSI bus DIOM controls whether that data goes to I...

Page 233: ...The upper Dword address will be fetched along with the instruction and loaded into the Dynamic Block Move Selector DBMS register If the EN64DBMV bit is cleared then the upper Dword address is pulled f...

Page 234: ...ting each address individually Note Using indirect and table indirect addressing simultaneously is not permitted use only one addressing method at a time TIA Table Indirect 28 32 Bit Addressing When t...

Page 235: ...brought into the LSI53C896 Execution of the move begins at this point SCRIPTS can directly execute operating system I O data structures saving time at the beginning of an I O operation The I O data s...

Page 236: ...et loaded into the DMA Next Address 64 DNAD64 automatically Note If EN64TIBMV is set and 64TIMOD is set then bits 31 24 of the first Dword of the table entry where the byte count is located will be lo...

Page 237: ...bits 24 31 40 bit addressing only Index Value Selector Used 0x00 Scratch C 0x01 Scratch D 0x02 Scratch E 0x03 Scratch F 0x04 Scratch G 0x05 Scratch H 0x06 Scratch I 0x07 Scratch J 0x08 Scratch K 0x09...

Page 238: ...decodes its SCSI Group Code If the SCSI Group Code is either Group 0 Group 1 Group 2 or Group 5 then the LSI53C896 overwrites the DMA Byte Counter DBC register with the length of the Command Descript...

Page 239: ...If the SATN signal is asserted by the initiator or a parity error occurred during the transfer it is possible to halt the transfer and generate an interrupt The Disable Halt on Parity Error or ATN bi...

Page 240: ...T1 register the LSI53C896 generates a phase mismatch interrupt and the instruction is not executed During a Message Out phase after the LSI53C896 has performed a select with Attention or SATN is manua...

Page 241: ...ion the DMA Next Address DNAD register is incremented by the number of bytes transferred This process is repeated until the DBC register is decremented to zero At this time the LSI53C896 fetches the n...

Page 242: ...o an address in memory that points to the data location When bit 28 is set indicating table indirect addressing the value in this field is an offset into a table pointed to by the Data Structure Addre...

Page 243: ...ion 5 4 Read Write Instructions Target Mode Reselect Instruction The LSI53C896 arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID SCID register If it loses arbitration it...

Page 244: ...ches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register If reselected the LSI53C896 fetches the next instruction from the address pointed to by the 32 bit jump ad...

Page 245: ...n during the next available arbitration cycle without reporting any lost arbitration status If the LSI53C896 wins arbitration it attempts to select the SCSI device whose ID is defined in the destinati...

Page 246: ...Next Address DNAD register Manually set the LSI53C896 to the target mode when it is selected If the LSI53C896 is reselected it fetches the next instruction from the address pointed to by the DMA SCRI...

Page 247: ...and synchronous period are loaded from this address Prior to the start of an I O load the Data Structure Address DSA with the base address of the I O data structure Any address on a Dword boundary is...

Page 248: ...e indirect method Relative Uses the device ID in the instruction but treats the alternate address as a relative jump Table Relative Treats the alternate jump address as a relative jump and fetches the...

Page 249: ...nstruction R Reserved 15 11 CA Set Clear Carry 10 This bit is used in conjunction with a Set or Clear instruction to set or clear the Carry bit Setting this bit with a Set instruction asserts the Carr...

Page 250: ...3C896 is operating as an initiator or the SCSI Loopback Enable bit is set in the SCSI Test Two STEST2 register The Set Clear SCSI ACK ATN instruction is used after message phase Block Move operations...

Page 251: ...e 29 27 The combinations of these bits determine if the instruction is a Read Write or an I O instruction Opcodes 0b000 through 0b100 are considered I O instructions O 2 0 Operator 26 24 These bits ar...

Page 252: ...Add operation is used to increment or decrement register values or memory values if used in conjunction with a Memory to Register Move operation for use as loop counters Subtraction is not available w...

Page 253: ...he left and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA SHL SFBR Shift the SFBR register one bit to the left and place the result in the register Syntax Move SFBR S...

Page 254: ...a to register without carry and place the result in the same register Syntax Move RegA data8 to RegA Add data to register without carry and place the result in the SCSI First Byte Received SFBR regist...

Page 255: ...Instruction The LSI53C896 can do a true false comparison of the ALU carry bit or compare the phase and or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons...

Page 256: ...ster Since the TEMP register is not a stack and can only hold one Dword nested call instructions are not allowed If the comparisons are false the LSI53C896 fetches the next instruction from the addres...

Page 257: ...rred The LSI53C896 halts and the DMA SCRIPTS Pointer DSP register must be written to before starting any further operation Interrupt on the Fly Instruction The LSI53C896 can do a true false comparison...

Page 258: ...Address Start execution at the current address plus or minus the relative offset The SCRIPTS program counter is a 32 bit value pointing to the SCRIPTS currently under execution by the LSI53C896 The ne...

Page 259: ...2 64 Bit Jump 22 When this bit is cleared the jump address is 32 bits wide When this bit is set the jump address is 64 bits wide CT Carry Test 21 When this bit is set decisions based on the ALU carry...

Page 260: ...the compare occurs When the LSI53C896 is operating in the target mode and this bit is set it tests for an active SCSI SATN signal VP Wait For Valid Phase 16 If the Wait for Valid Phase bit is set the...

Page 261: ...10 Transfer Control Instructions Second Dword Jump Address 31 0 This 32 bit field contains the address of the next instruction to fetch when a jump is taken Once the LSI53C896 fetches the instruction...

Page 262: ...emory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers Up to 16 Mbytes may be transferred with one instruction There are two...

Page 263: ...tch Enable bit in the DMA Control DCNTL register is set For information on SCRIPTS instruction prefetching see Chapter 2 Functional Description TC 23 0 Transfer Count 23 0 The number of bytes to trans...

Page 264: ...with a byte stored in system memory first move the byte to an intermediate LSI53C896 register for example a SCRATCH register and then to the SCSI First Byte Received SFBR The same address alignment re...

Page 265: ...store instructions are represented by two Dword opcodes The first Dword contains the DMA Command DCMD and DMA Byte Counter DBC register values The second Dword contains the DMA SCRIPTS Pointer Save D...

Page 266: ...he DMA Mode DMODE register determine whether the destination or source address of the instruction is in Memory space or I O space as illustrated in the following table The Load Store utilizes the PCI...

Page 267: ...ng the prefetch unit When this bit is cleared the Store instruction automatically flushes the prefetch unit Use No Flush if the source and destination are not within four instructions of the current S...

Page 268: ...ore Instructions Second Dword Memory I O Address DSA Offset 31 0 This is the actual memory location of where to load store or the offset from the Data Structure Address DSA register value 31 24 23 0 D...

Page 269: ...ion 6 1 DC Characteristics Section 6 2 TolerANT Technology Electrical Characteristics Section 6 3 AC Characteristics Section 6 4 PCI and External Memory Interface Timing Diagrams Section 6 5 SCSI Timi...

Page 270: ...N Input voltage VSS 0 3 VDD 0 3 V VIN5V Input voltage 5 V tolerant pins VSS 0 3 5 25 V ILP 2 2 2 V VPIN 8 V Latch up current 150 mA ESD3 3 SCSI pins only Electrostatic discharge 2 K V MIL STD 883C Met...

Page 271: ...ts Test Conditions IO Source current 7 13 mA Asserted state IO Sink current 7 13 mA Asserted state IO Source current 3 5 6 5 mA Negated state IO Sink current 3 5 6 5 mA Negated state IOZ 3 state leaka...

Page 272: ...Note 1 VIL SE sense voltage VSS 0 3 0 5 V Note 1 IOZ Input leakage 10 10 A VPIN 0 V 5 25 V 1 Functional test specified for each mode VIH VS VIL See A_DIFFSENS and B_DIFFSENS signal descriptions on pag...

Page 273: ...L Output low voltage VSS 0 4 V 8 mA dynamic IOZ 3 state leakage 10 10 A VPIN 0 V 5 25 V IPULL Pull down current 7 5 75 A 1 For channels A and B except MAD 7 0 Table 6 8 Output Signals MAS 1 0 MCE MOE...

Page 274: ...tage 0 55 V 16 mA IOZ 3 state leakage 10 10 A VPIN 0 V 5 25 V IPULL DOWN Pull down current1 7 5 75 A 1 Pull down test does not apply to AD 31 0 and C_BE 3 0 Table 6 10 Input Signals CLK GNT IDSEL INT_...

Page 275: ...voltage 0 1 VDD V 1500 A VOH 5 V Tolerant output high voltage 2 4 V 16 mA VOL 5 V Tolerant output low voltage 0 55 V 16 mA IOZ 3 state leakage 10 10 A VPIN 0 V 5 25 V IPULL UP Pull up current1 75 7 5...

Page 276: ...s Test Conditions VOH 2 Output high voltage 2 0 VDD V IOH 7 mA VOL Output low voltage VSS 0 5 V IOL 48 mA VIH Input high voltage 2 0 VDD 0 3 V VIL Input low voltage VSS 0 3 0 8 V Referenced to VSS VIK...

Page 277: ...re 6 4 Ultra filter delay 10 15 ns Figure 6 4 Ultra2 filter delay 5 8 ns Figure 6 4 Extended filter delay 40 60 ns Figure 6 4 1 These values are guaranteed by periodic characterization they are not 10...

Page 278: ...CSI Receivers Figure 6 6 Input Current as a Function of Input Voltage 1 0 Received Logic Level Input Voltage Volts 1 1 1 3 1 5 1 7 40 20 0 20 40 4 0 4 8 12 16 0 7 V 8 2 V HIGH Z OUTPUT ACTIVE Input Vo...

Page 279: ...efer to Section 6 1 DC Characteristics Chip timing is based on simulation at worst case voltage temperature and processing Timing was developed with a load capacitance of 50 pF Table 6 14 and Figure 6...

Page 280: ...Symbol Parameter Min Max Units t1 Bus clock cycle time 30 DC ns SCSI clock cycle time SCLK 2 2 This parameter must be met to ensure SCSI timing is within specification 25 60 ns t2 CLK LOW time3 3 Duty...

Page 281: ...e 6 15 Reset Input Symbol Parameter Min Max Units t1 Reset pulse width 10 tCLK t2 Reset deasserted setup to CLK HIGH 0 ns t3 MAD setup time to CLK HIGH for configuring the MAD bus only 20 ns t4 MAD ho...

Page 282: ...t Timing The second group applies to Initiator Timing The third group applies to External Memory Timing Note Multiple byte accesses to the external memory bus increase the read or write cycle by 11 cl...

Page 283: ...Burst Write 32 Bit Address and Data Burst Write 64 Bit Address and Data External Memory Timing External Memory Read External Memory Write Normal Fast Memory 128 Kbytes Single Byte Access Read Cycle N...

Page 284: ...t3 CLK to shared signal output valid 11 ns Data Out Byte Enable Addr In t2 In Out t1 t2 t1 t3 t2 t1 t1 t2 t2 t3 t3 t2 t1 t3 t2 t1 CLK Driven by System FRAME Driven by System AD 31 0 Driven by Master...

Page 285: ...7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns Data In Byte Enable Addr In t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 t2 t1 CLK Driven by System FRAME Driven by Mas...

Page 286: ...ignal input hold time 0 ns t3 CLK to shared signal output valid 11 ns Data Byte Enable Addr In t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME Driven by Master AD 31 0 Driven by Mast...

Page 287: ...2 t1 t2 t1 t2 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME Driven by Master AD 31 0 Driven by Master Addr C_BE 3 0 Driven by Master PAR PAR64 Driven by Master Addr IRDY Driven by Master TRDY Driven by...

Page 288: ...me 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns Byte Enable Addr In CMD t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME Driven by Master AD 3...

Page 289: ...valid 11 ns Byte Enable t2 t1 t2 t1 t2 t1 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME Driven by Master AD 31 0 Driven by Master C_BE 3 0 Driven by Master PAR PAR64 Driven by Master IRDY Driven by Mas...

Page 290: ...Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time...

Page 291: ...n by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t8 t6 t3 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI53C896...

Page 292: ...hared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CLK to side signal output valid 12 ns t7 CLK...

Page 293: ...Driven by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t8 t6 t3 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI5...

Page 294: ...red signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CLK to...

Page 295: ...by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t6 t3 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI53C896 t3 C...

Page 296: ...ared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CLK to...

Page 297: ...riven by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t6 t3 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI53C896 t...

Page 298: ...ifications Table 6 27 Burst Read 32 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid...

Page 299: ...896 GPIO1_MASTER Driven by LSI53C896 REQ Driven by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI5...

Page 300: ...8 Burst Read 64 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t10 CLK HIG...

Page 301: ...riven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI53C896 t3 GNT Driven by Arbiter FRAME Driven by LSI53C896 Addr...

Page 302: ...9 Burst Write 32 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t10 CLK HI...

Page 303: ...ven by LSI53C896 GPIO1_MASTER Driven by LSI53C896 REQ Driven by LSI53C896 PAR Driven by LSI53C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 D...

Page 304: ...0 Burst Write 64 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t10 CLK HI...

Page 305: ...3C896 IRDY Driven by LSI53C896 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by LSI53C896 t3 GNT Driven by Arbiter FRAME Driven by LSI...

Page 306: ...6 38 Specifications This page intentionally left blank...

Page 307: ...ax Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns t11 Address setup to MAS HIGH 25 ns t12 Address hold from MAS HIGH 15 ns...

Page 308: ...y Master Addr C_BE 3 0 Driven by Master FRAME Driven by Master Data Driven by Memory 1 2 3 4 5 6 7 8 9 10 LSI53C896 Data Addr In Byte Enable LSI53C896 Data MAD Addr drvn by LSI53C896 High Order Addres...

Page 309: ...53C896 DEVSEL Driven by LSI53C896 AD 31 0 Driven by Master Addr C_BE 3 0 Driven by Master FRAME Driven by Master Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 LSI53C896 Data Data Out LSI53C896 D...

Page 310: ...6 42 Specifications This page intentionally left blank...

Page 311: ...t hold time 0 ns t3 CLK to shared signal output valid 11 ns t11 Address setup to MAS HIGH 25 ns t12 Address hold from MAS HIGH 15 ns t13 MAS pulse width 25 ns t20 Data setup to MWE LOW 30 ns t21 Data...

Page 312: ...by Master FRAME Driven by Master 1 2 3 4 5 6 7 8 9 10 Addr In MAD Driven by LSI53C896 High Order Address Middle Order Address Low Order Address MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE D...

Page 313: ...OP Driven by LSI53C896 DEVSEL Driven by LSI53C896 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by...

Page 314: ...ocked in 160 ns t15 Address valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup...

Page 315: ...ngle Byte Access Read Cycle Cont CLK Driven by System Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 MAD Addr driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driven by L...

Page 316: ...setup to MWE LOW 30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 75 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE...

Page 317: ...Kbytes Single Byte Access Write Cycle Cont CLK Driven by System 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driven by LSI53C896 MOE Dri...

Page 318: ...ven by LSI53C896 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by Master FRAME Driven by Master Master Addr Data Master Addr Data MAD Addr Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI...

Page 319: ...by LSI53C896 DEVSEL Driven by LSI53C896 AD 31 0 Driven by LSI53C896 C_BE 3 0 Driven by Master FRAME Driven by Master Master Addr Data Master Addr Data MAD Addr Driven by LSI53C896 MAS1 Driven by LSI5...

Page 320: ...Driven by LSI53C896 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driven by LSI53C896 MOE Driven by LSI53C896...

Page 321: ...SI53C896 STOP Driven by LSI53C896 DEVSEL Driven by LSI53C896 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driv...

Page 322: ...ress valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5 ns CLK Dr...

Page 323: ...s Read Cycle Cont CLK Driven by System Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 MAD Addr driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driven by LSI53C896 MOE Dr...

Page 324: ...1 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 75 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE HIGH 25 ns CLK Driven by S...

Page 325: ...ry 128 Kbytes Write Cycle Cont CLK Driven by System 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C896 MAS1 Driven by LSI53C896 MAS0 Driven by LSI53C896 MCE Driven by LSI53C896 MOE Driven by LSI53C...

Page 326: ...ked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5 ns CLK Driven by System 1 2 3 4...

Page 327: ...30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 75 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE HIGH 25 ns CLK Dr...

Page 328: ...igure 6 35 Initiator Asynchronous Send Table 6 39 Initiator Asynchronous Send Symbol Parameter Min Max Units t1 SACK asserted from SREQ asserted 5 ns t2 SACK deasserted from SREQ deasserted 5 ns t3 Da...

Page 329: ...asserted 5 ns t3 Data setup to SREQ asserted 0 ns t4 Data hold from SACK asserted 0 ns Valid n Valid n 1 n 1 n 1 n n t1 t2 t3 t4 SREQ SACK SD 15 0 SDP 1 0 Table 6 41 Target Asynchronous Send Symbol Pa...

Page 330: ...synchronous Receive Symbol Parameter Min Max Units t1 SREQ deasserted from SACK asserted 5 ns t2 SREQ asserted from SACK deasserted 5 ns t3 Data setup to SACK asserted 0 ns t4 Data hold from SREQ deas...

Page 331: ...s t5 Receive data setup to SREQ or SACK asserted 0 ns t6 Receive data hold from SREQ or SACK asserted 45 ns Table 6 44 SCSI 1 Transfers Differential 4 17 Mbytes Symbol Parameter Min Max Units t1 Send...

Page 332: ...Mbytes 16 Bit Transfers 50 MHz Clock1 1 Transfer period bits bits 6 4 in the SCSI Transfer SXFER register are set to zero and the Extra Clock Cycle of Data Setup bit bit 7 in SCSI Control One SCNTL1 i...

Page 333: ...s t4 Send data hold from SREQ or SACK asserted 17 ns t5 Receive data setup to SREQ or SACK asserted 0 ns t6 Receive data hold from SREQ or SACK asserted 6 ns Table 6 48 Ultra SCSI HVD Transfers 20 0 M...

Page 334: ...Extend REQ ACK Filtering bit SCSI Test Two STEST2 bit 1 has no effect Min Max Unit t1 Send SREQ or SACK assertion pulse width 8 ns t2 Send SREQ or SACK deassertion pulse width 8 ns t1 Receive SREQ or...

Page 335: ...e Drawings The signal names are listed alphabetically in Table 6 50 and numerically in Table 6 51 The signal locations on the 329 Ball Grid Array BGA are illustrated in Figure 6 40 Figure 6 41 is the...

Page 336: ...B_SD1 G23 B_SD1 H21 B_SD2 H20 B_SD2 H22 B_SD3 H23 B_SD3 J21 B_SD4 J20 B_SD4 J22 B_SD5 J23 B_SD5 K21 B_SD6 L20 B_SD6 K22 B_SD7 K23 B_SD7 L21 B_SD8 V21 B_SD8 W23 B_SD9 W22 B_SD9 W20 B_SD10 W21 B_SD10 Y2...

Page 337: ...VSS D12 A_SRST D13 VDD D14 A_SSEL D15 A_SREQ2 D16 VDD D17 A_SD9 D18 A_SD11 D19 VSS D20 NC D21 B_SD12 D22 B_SD12 D23 TDO E1 TDI E2 TMS E3 VDD CORE E4 B_SD13 E20 B_SD13 E21 B_SD14 E22 B_SD14 E23 ALT_INT...

Page 338: ...6 70 Specifications Figure 6 40 LSI53C896 329 BGA Bottom View...

Page 339: ...Mechanical Drawing Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representative by...

Page 340: ...6 72 Specifications...

Page 341: ...C 0x23 Read Write 4 10 Base Address Register Zero I O 0x10 0x13 Read Write 4 9 Bridge Support Extensions PMCSR_BSE 0x46 Read Only 4 18 Cache Line Size 0x0C Read Write 4 7 Capabilities Pointer 0x34 Rea...

Page 342: ...Read Only 4 12 Subsystem Vendor ID 0x2C 0x2D Read Only 4 11 Vendor ID 0x00 0x01 Read Only 4 2 SCSI Registers Adder Sum Output ADDER 0x3C 0x3F Read Only 4 75 Chip Control 0 CCNTL0 0x56 Read Write 4 10...

Page 343: ...0x2F Read Write 4 66 DMA SCRIPTS Pointer Save DSPS 0x30 0x33 Read Write 4 67 DMA Status DSTAT 0x0C Read Only 4 41 DSA Relative Selector DRS 0xAC 0xAF Read Write 4 109 Dynamic Block Move Selector DBMS...

Page 344: ...atch Register A SCRATCHA 0x34 0x37 Read Write 4 68 Scratch Register B SCRATCHB 0x5C 0x5F Read Write 4 105 Scratch Registers C R SCRATCHC SCRATCHR 0x60 0x9F Read Write 4 106 SCRIPTS Fetch Selector SFS...

Page 345: ...SCSI Status One SSTAT1 0x0E Read Only 4 45 SCSI Status Two SSTAT2 0x0F Read Only 4 47 SCSI Status Zero SSTAT0 0x0D Read Only 4 44 SCSI Test Four STEST4 0x52 Read Only 4 100 SCSI Test One STEST1 0x4D R...

Page 346: ...A 6 Register Summary...

Page 347: ...e external memory interface diagrams Figure B 1 16 Kbyte Interface with 200 ns Memory LSI53C896 27C128 MOE OE MCE CE D 7 0 8 MAD 7 0 Bus CK Q 7 0 8 A 7 0 QE D 5 0 CK Q 5 0 QE 6 A 13 8 6 VDD MAS0 MAS1...

Page 348: ...0 8 MAD 7 0 Bus CK Q 7 0 8 A 7 0 QE D 5 0 CK Q 5 0 QE 6 A 15 8 6 VDD MAS0 MAS1 8 Note MAD 3 1 0 pulled LOW internally MAD bus sense logic enabled for 64 Kbyte of fast memory 150 ns devices 33 MHz HCT3...

Page 349: ...Q 5 0 QE 6 A 15 8 6 VDD MAS0 MAS1 8 Note MAD 2 0 pulled LOW internally MAD bus sense logic enabled for 128 256 512 Kbytes or 1 Mbyte of fast memory 150 ns devices 33 MHz The HCT374s may be replaced wi...

Page 350: ...d for 512 Kbytes of slow memory 150 ns devices additional time required for HCT139 33 MHz The HCT374s may be replaced with HCT377s HCT374 HCT374 GPIO4 MWE VPP Control 12 V VPP Optional for Flash Memor...

Page 351: ...4 72 CM 4 56 CMP 2 46 4 76 4 80 COM 4 74 CON 4 25 4 51 CP 4 13 CSBC 4 115 CSF 2 48 4 98 CTEST0 4 55 CTEST1 4 55 CTEST2 4 56 CTEST3 4 58 CTEST4 4 61 CTEST5 4 63 CTEST6 4 64 CTYPE 4 85 D1S 4 17 D2S 4 17...

Page 352: ...4 71 ME 4 85 MEMORY 4 9 MG 4 15 ML 4 15 MMRS 4 107 MMWS 4 108 MO 4 0 4 35 MPEE 4 61 MSG 4 39 4 41 4 47 NC 4 6 NIP 4 16 OLF 4 44 OLF1 4 48 ORF 4 44 ORF1 4 47 PAR 4 77 4 81 PCICIE 4 56 PEN 4 18 PFEN 4 7...

Page 353: ...5 31 32 bit addressing 5 6 3 State 3 3 64 Kbytes ROM read cycle 6 58 6 59 64 bit addressing 5 7 addressing in SCRIPTS 2 22 SCRIPT selectors 4 107 table indirect indexing mode 64TIMOD 4 104 8 bit 16 b...

Page 354: ...st read 32 bits address and data 6 30 64 bits address and data 6 32 burst write 32 bits address and data 6 34 64 bits address and data 6 36 bus command and byte enables 3 6 fault BF 4 42 4 71 byte cou...

Page 355: ...2 30 2 44 DF 7 0 4 64 DFIFO 4 59 byte offset counter bits 9 8 BO 9 8 4 64 empty DFE 4 41 sections 2 31 size DFS 4 63 interrupt 2 45 2 46 2 48 enable DIEN 2 28 2 45 2 46 4 71 interrupt pending DIP 4 52...

Page 356: ...hing with LVD and single ended mode 2 35 description 2 36 HVD or SE LVD DIF 4 95 HVD signals 2 36 I I O 3 3 instructions 5 15 read command 2 6 space 2 3 write command 2 6 IDSEL 2 3 3 8 signal 2 6 ille...

Page 357: ...22 mailbox one MBOX1 2 43 4 54 mailbox zero MBOX0 2 43 4 54 manual start mode MAN 4 70 MAS0 3 19 MAS1 3 19 masking 2 46 master control for set or reset pulses MASR 4 63 data parity error MDPE 4 42 4...

Page 358: ...PMJAD1 4 111 jump address 2 PMJAD2 4 111 jump registers 4 111 physical dword address and data 3 6 PME clock PMEC 4 17 enable PEN 4 18 status PST 4 17 support PMES 4 16 polling 2 43 power and ground s...

Page 359: ...SIEN0 2 28 2 45 4 76 interrupt pending SIP 4 52 interrupt status one SIST1 2 44 2 45 2 47 2 49 4 82 interrupt status zero SIST0 2 28 2 44 2 45 2 47 2 49 4 79 interrupts 2 48 isolation mode ISO 4 93 lo...

Page 360: ...ed interrupts 2 47 start address 5 14 5 22 DMA operation STD 4 74 SCSI transfer SST 4 26 sequence START 4 22 static block move selector SBMS 4 109 status register 4 5 STOP command 2 10 stop signal 3 8...

Page 361: ...40 MHz clock 6 66 unexpected disconnect UDC 4 77 4 81 updated address UA 4 113 upper register address line A7 5 24 use data8 SFBR 5 23 V VDD 3 21 A 3 21 Bias 3 21 Bias2 3 21 Core 3 21 vendor ID VID 4...

Page 362: ...IX 12 Index...

Page 363: ...age add your comments and fax it to us at the number shown If appropriate please also fax copies of any marked up pages from this document Important Please include your name phone number fax number an...

Page 364: ...ror and page number If appropriate please fax a marked up copy of the page s Please complete the information below so that we may contact you directly for clarification or additional information Excel...

Page 365: ...727 507 5000 Georgia Atlanta A E Tel 770 623 4400 B M Tel 770 980 4922 W E Tel 800 876 9953 Duluth I E Tel 678 584 0812 Hawaii A E Tel 800 851 2282 Idaho A E Tel 801 365 3800 W E Tel 801 974 9953 Ill...

Page 366: ...781 271 9953 South Carolina A E Tel 919 872 0712 W E Tel 919 469 1502 South Dakota A E Tel 800 829 0116 W E Tel 612 853 2280 Tennessee W E Tel 256 830 1119 East West A E Tel 800 241 8182 Tel 800 633...

Page 367: ...Tel 317 984 8608 Ligonier R A Tel 219 894 3184 Plainfield R A Tel 317 838 0360 Massachusetts Burlington SGY Tel 781 238 0870 Michigan Byron Center R A Tel 616 554 1460 Good Rich R A Tel 810 636 6060...

Page 368: ...ton Mint Technology 77 South Bedford Street Burlington MA 01803 Tel 781 685 3800 Fax 781 685 3801 Minnesota Minneapolis 8300 Norman Center Drive Suite 730 Minneapolis MN 55437 Tel 612 921 8300 Fax 612...

Page 369: ...Singapore Singapore LSI Logic Pte Ltd 7 Temasek Boulevard 28 02 Suntec Tower One Singapore 038987 Tel 65 334 9061 Fax 65 334 4749 Sweden Stockholm LSI Logic AB Finlandsgatan 14 164 74 Kista Tel 46 8...

Page 370: ...ei Time24 Bldg 35 Tansu cho Shinjuku ku Tokyo 162 0833 Tel 81 3 3260 1411 Fax 81 3 3260 7100 Technical Center Tel 81 471 43 8200 Marubeni Solutions 1 26 20 Higashi Shibuya ku Tokyo 150 0001 Tel 81 3 5...

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