LSI LSI53C896, Technical Manual

Page: 14 / 370

xiv Contents
6.8 Output Signals—MAS/[1:0], MCE/, MOE/_TESTOUT,
MWE/, TDO
6-5
6.9 Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64,
REQ64/, ACK64/
6-6
6.10 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS
6-6
6.11 Output Signals—INTA, INTB, ALT_INTA, ALT_INTB,
REQ/
6-7
6.12 Output Signal—SERR/ 6-7
6.13 TolerANT Technology Electrical Characteristics for SE
SCSI Signals
6-8
6.14 External Clock 6-12
6.15 Reset Input 6-13
6.16 Interrupt Output 6-14
6.17 PCI Configuration Register Read 6-16
6.18 PCI Configuration Register Write 6-17
6.19 Operating Register/SCRIPTS RAM Read, 32-Bit 6-18
6.20 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19
6.21 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20
6.22 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21
6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22
6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-24
6.25 Back to Back Read, 32-Bit Address and Data 6-26
6.26 Back to Back Write, 32-Bit Address and Data 6-28
6.27 Burst Read, 32-Bit Address and Data 6-30
6.28 Burst Read, 64-Bit Address and Data 6-32
6.29 Burst Write, 32-Bit Address and Data 6-34
6.30 Burst Write, 64-Bit Address and Data 6-36
6.31 External Memory Read 6-39
6.32 External Memory Write 6-43
6.33 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-46
6.34 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-48
6.35 Slow Memory (
≥
128 Kbytes) Read Cycle 6-54
6.36 Slow Memory (
≥
128 Kbytes) Write Cycle 6-56
6.37
≤
64 Kbytes ROM Read Cycle 6-58
*