LSI LSI53C896, Technical Manual

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x Contents
Chapter 6 Specifications
6.1 DC Characteristics 6-1
6.2 TolerANT Technology Electrical Characteristics 6-8
6.3 AC Characteristics 6-11
6.4 PCI and External Memory Interface Timing Diagrams 6-14
6.4.1 Target Timing 6-15
6.4.2 Initiator Timing 6-22
6.4.3 External Memory Timing 6-39
6.5 SCSI Timing Diagrams 6-60
6.6 Package Drawings 6-67
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples
Index
Customer Feedback
Figures
1.1 Typical LSI53C896 System Application 1-2
1.2 Typical LSI53C896 Board Application 1-3
2.1 LSI53C896 Block Diagram 2-2
2.2 Parity Checking/Generation 2-30
2.3 DMA FIFO Sections 2-31
2.4 LSI53C896 Host Interface SCSI Data Paths 2-32
2.5 8-Bit HVD Wiring Diagram for Ultra SCSI 2-37
2.6 Regulated Termination for Ultra2 SCSI 2-39
2.7 Determining the Synchronous Transfer Rate 2-41
2.8 Interrupt Routing Hardware Using the LSI53C896 2-51
2.9 Block Move and Chained Block Move Instructions 2-53
3.1 LSI53C896 Functional Signal Grouping 3-2
5.1 SCRIPTS Overview 5-4
5.2 Block Move Instruction - First Dword 5-5
5.3 Block Move Instruction - Second Dword 5-14
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