LSI LSI53C896, Technical Manual

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2-8 Functional Description
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.1 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowable burst size determined from the
DMA Mode (DMODE) burst size
bits, and the Chip Test Five (CTEST5) , bit 2.
2.1.2.11 DAC Command
The LSI53C896 performs DACs when 64-bit addressing is required. See
PCI specification 2.1. If any of the selector registers contain a nonzero
value, a DAC will be generated.
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading to a cache line boundary rather than
a single memory cycle. The Read Line function in the LSI53C896 takes
advantage of the PCI 2.1 specification regarding issuing of this
command.
If the cache mode is disabled, Read Line commands will not be issued.
If the cache mode is enabled, a Read Line command is issued on all
read cycles, except nonprefetch opcode fetches, when the following
conditions are met:
•
The CLSE (Cache Line Size Enable, bit 7, of the DMA Control
(DCNTL) register) and ERL (Enable Read Line, bit 3, of the DMA
Mode (DMODE) register) bits are set.
•
The Cache Line Size register for each function must contain a legal
burst size value in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value
is less than or equal to the DMODE burst size.
•
The transfer will cross a Dword boundary but not a cache line
boundary.
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