LSI LSI53C896, Technical Manual

Page: 184 / 370

4-72 Registers
The INTA/ and INTB/ outputs are latched. Once asserted, they remain
asserted until the interrupt is cleared by reading the appropriate status
register. Masking an interrupt after the INTA/, or INTB/, output is asserted
does not cause deassertion of INTA/, or INTB/.
For more information on interrupts, see Chapter 2, “Functional
Description.”
Register: 0x3A
Scratch Byte Register (SBR)
Read/Write
SBR Scratch Byte Register [7:0]
This is a general purpose register. Apart from CPU
access, only register read/write and memory moves into
this register alter its contents. The default value of this
register is zero. This register is called the DMA Watchdog
Timer on previous LSI53C8XX family products.
Register: 0x3B
DMA Control (DCNTL)
Read/Write
CLSE Cache Line Size Enable 7
Setting this bit enables the LSI53C896 SCSI function to
sense and react to cache line boundaries set up by the
DMA Mode (DMODE) or PCI Cache Line Size register,
whichever contains the smaller value. Clearing this bit
disables the cache line size logic and the LSI53C896
SCSI function monitors the cache line size using the
DMODE register.
7 0
SBR
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
CLSE PFF PFEN SSM IRQM STD IRQD COM
0 0 0 0 0 0 0 0
*