LSI LSI53C896, Technical Manual

Page: 192 / 370

4-80 Registers
CMP Function Complete 6
This bit is set when an arbitration only or full arbitration
sequence is completed.
SEL Selected 5
This bit is set when the LSI53C896 SCSI function is
selected by another SCSI device. The Enable Response
to Selection bit must be set in the
SCSI Chip ID (SCID)
register (and the Response ID Zero (RESPID0) and
Response ID One (RESPID1) registers must hold the
chip’s ID) for the LSI53C896 SCSI function to respond to
selection attempts.
RSL Reselected 4
This bit is set when the LSI53C896 SCSI function is
reselected by another SCSI device. The Enable
Response to Reselection bit must be set in the
SCSI
Chip ID (SCID) register (and the Response ID Zero
(RESPID0) and Response ID One (RESPID1) registers
must hold the chip’s ID) for the LSI53C896 SCSI function
to respond to reselection attempts.
SGE SCSI Gross Error 3
This bit is set when the LSI53C896 SCSI function
encounters a SCSI Gross Error Condition. The following
conditions can result in a SCSI Gross Error Condition:
•
Data Underflow – reading the SCSI FIFO when no
data is present.
•
Data Overflow – writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting
the SCSI FIFO.
•
Offset Underflow – the LSI53C896 SCSI function is
operating in the target mode and a SACK/ pulse is
received when the outstanding offset is zero.
•
Offset Overflow – the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the
maximum synchronous offset defined by the
SCSI
Transfer (SXFER) register.
•
A phase change occurs with an outstanding
synchronous offset when the LSI53C896 SCSI
function is operating as an initiator.
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