LSI LSI53C896, Technical Manual

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PCI Functional Description 2-9
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line. That is, the master intends to write
all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI
Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C896 enables Memory Write and Invalidate cycles
when bit 0 (WRIE) in the
Chip Test Three (CTEST3) register and bit 4
(WIE) in the PCI Command register are set. When the following
conditions are met, Memory Write and Invalidate commands are issued:
•
The CLSE bit (Cache Line Size Enable, bit 7, of the DMA Control
(DCNTL) register), WRIE bit (Write and Invalidate Enable, bit 0, of
the Chip Test Three (CTEST3) register), and PCI configuration
Command register, bit 4 are set.
•
The Cache Line Size register for each function contains a legal burst
size value in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is
less than or equal to the
DMA Mode (DMODE) burst size.
•
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C896 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
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