LSI LSI53C896, Technical Manual

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PCI Configuration Registers 4-17
D2S D2_Support 10
The LSI53C896 sets this bit to indicate support for power
management state D2.
D1S D1_Support 9
The LSI53C896 sets this bit to indicate support for power
management state D1.
AUXC Aux_Current [8:6]
The LSI53C896 always returns zeros. This feature is not
supported.
DSI Device Specific Initialization 5
This bit is cleared to indicate that the LSI53C896 requires
no special initialization before the generic class device
driver is able to use it.
R Reserved 4
PMEC PME Clock 3
Bit 3 is cleared because the LSI53C896 does not provide
a PME pin.
VER[2:0] Version [2:0]
These three bits are set to 0b010 to indicate that the
LSI53C896 complies with Revision 1.1 of the PCI Power
Management Interface Specification.
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
PST PME_Status 15
The LSI53C896 always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
DSCL[1:0] Data_Scale [14:13]
The LSI53C896 does not support the Data register.
Therefore, these two bits are always cleared.
15 14 13 12 9 8 7 2 0
PST DSCL[1:0] DSLT[3:0] PEN R PWS[1:0]
0 0 0 0 0 0 0 0 x x x x x x 0 0
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