Hioki 3504-40 C HiTester, Instruction Manual

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8.6 Things to Know before Beginning Communication
148
Status Byte Register (STB) ______________________________________
A status byte register is an 8-bit register output from the unit to the controller dur-
ing serial polling. If even one of the status byte register bits enabled by the ser-
vice request enable register changes from "0" to "1," the MSS bit becomes 1. At
the same time, the SRQ bit also becomes "1" and a service request is gener-
ated.
The SRQ bit is always synchronized with the service request and only read and
simultaneously cleared upon being serial polled. The MSS bit is only read by an
"
* STB?
" query and is not cleared until the event is cleared by a command
such as a "
*
CLS
" command.
Service Request Enable Register (SRER) __________________________
When the service request enable register is used to set each of the bits to "1,"
the corresponding bits are enabled in the status byte register.
Bit 7
Unused
Bit 6
SRQ
This becomes 1 when a service request is sent.
MSS
This indicates logical OR of other bits of the status byte register.
Bit 5
ESB Standard event summary (logical OR) bit
This indicates the logical OR of a standard event status register.
Bit 4
MAV
Message available
This indicates there is a message in the output queue.
Bit 3
ESB3
Event summary (logical OR) bit 3
This indicates the logical OR of event status register 3.
Bit 2
ESB2
Event summary (logical OR) bit 2
This indicates the logical OR of event status register 2.
Bit 1
ESB1
Event summary (logical OR) bit 1
This indicates the logical OR of event status register 1.
Bit 0
ESB0
Event summary (logical OR) bit 01
This indicates the logical OR of event status register 0.