Anritsu BERTWave MP2100B, Operation Manual, Page: 211 / 382

7.6 Setting Clock Recovery and Rate
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7.6 Setting Clock Recovery and Rate
The trigger clock synchronized with the input signal is required to collect
data.
With the Options 011, 012, or 014, the PPG or ED synchronizing clock
(Sync Out) can be used.
The clock can be generated from the signal input to the following
connectors if the Option 053, 054, 055 clock recovery units are added to
the BERTWave.
●
Option 053: CRU In connector on the front panel
●
Option 054: O/E Data In connector on the front panel
●
Option 055: Data/CRU In connector of ED1
In this case, connect CRU Out on the front panel to Trigger Clk In using a
coaxial cable.
After the trigger clock is input to the BERTWave, the bit rate, clock rate,
and divide rate is set.
The bit rate is the signal input to Ch A or Ch B.
The clock rate is the frequency of the trigger clock.
Divide Rate is the rate between data bit rate and clock rate.
The value should be inputted to complete the following formula.
Bit Rate = Clock Rate × Divide Rate
CAUTION
● The impedance of the Trigger Clk In connector is 50 Ω .
Measurement may not be performed correctly if a cable
with another impedance is used.
● The amplitude of the signal input to the Trigger Clk In
connector is 2 Vp-p max. This is equivalent to + 10 dBm
for a sine-wave signal. Inputting a signal with a larger
voltage risks damaging the internal circuits.