Anritsu BERTWave MP2100B, Operation Manual, Page: 172 / 382

Chapter 6 Measuring Bit Error
6-12
Logic
Select the positive logic (POS) or negative logic (NEG).
Logic POS
NEG
0
Voltage (V)
Input
waveform to
the Data In
connector
0
Input
waveform to
the Data In
connector
1 0 1 0 0 1 1 0 0
0 1 0 1 1 0 0 1 1
Time
Time
Figure 6.3-3 Values Defined as Input Waveform
Pattern
The ED compares the received bit string and the internally generated bit
stream bit-by-bit and evaluates it differences as it errors.
As a result, set the same pattern at the PPG and ED.
For PRBS, since it is possible to predict the bits received next from the
received bit string, the time required for pattern synchronization can be
much shorter than for a Programmable Pattern.
There are two synchronization methods depending on the pattern length
for Programmable Pattern.
SYNC Control: OFF The entire pattern bits and received bit string are
compared.
SYNC Control: ON When the pattern length is 128 bits or more, 64 bits
starting from the bit specified at Frame Position
and the received bit string are compared.
When all 64 bits are in agreement, the data from
bit 65 is compared. When the pattern length is 127
bits or less, the entire received bit string and data
are compared.
All data bits are compared and when the obtained bit error rate is lower
than the bit error rate is set at Auto Sync Threshold, pattern
synchronization is evaluated as having been obtained.