RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
193/844
lowpower_internal_cnt
[15:0]
Counts the number of idle cycles before memory self-refresh with
memory and controller clock gating low power mode.
Please refer to
for more details.
lowpower_power_down_cn
t [15:0]
Counts the number of idle cycles before either memory power-down or
power-down with memory clock gating low power mode.
Please refer to
for more details.
lowpower_refresh_enable
[1:0]
Sets whether refreshes will occur while the Memory Controller is in any
of the low power modes.
1'b0 - Refreshes still occur
1'b1 - Refreshes do not occur
Please refer to
for more details.
lowpower_refresh_hold
[15:0]
Sets the number of cycles that the Memory Controller will wait before
attempting to re-lock the DLL when using the controller clock gating
mode low power mode. This counter will ONLY be used in this mode,
the deepest low power mode.
When this counter expires, the DLL will be un-gated for at least 16
cycles during which the DLL will attempt to re-lock. After 16 cycles have
elapsed and the DLL has locked, the DLL controller clock will be gated
again and the counter will reset to this value. If the DLL requires more
than 16 cycles to re-lock, the un-gated time will be longer.
Please refer to
for more details.
lowpower_self_refresh_cnt
[15:0]
Counts the number of cycles to the next memory self-refresh low power
mode.
Please refer to
for more details.
max_col_reg [3:0]
Shows the maximum width of column address in the DRAM devices.
This value can be used to set the column_size parameter. This
parameter is read-only.
column_size = max_col_reg - <number of column bits in memory
device>.
max_cs_reg [1:0]
Defines the maximum number of chip selects for the Memory Controller
as the log2 of the number of chip selects.
max_row_reg [3:0]
Shows the maximum width of the memory address bus (number of row
bits) for the Memory Controller. This value can be used to set the
addr_pins parameter. This parameter is read-only.
addr_pins = max_row_reg - <number of row bits in memory device>.
no_cmd_init [0]
Disables DRAM commands until DLL initialization is complete and tdll
has expired.
1'b0 - Issue only REF and PRE commands during DLL initialization of
the DRAM devices.
1'b1 - Do not issue any type of command during DLL initialization of the
DRAM devices.
ocd_adjust_pdn_cs [4:0]
Sets the off-chip driver (OCD) pull-down adjustment settings for the
DRAM devices. The Memory Controller will issue OCD adjust
commands to the DRAM devices during power up.
Bits 3:0 - Number of OCD adjust commands to be issued.
Bit 4 - Increment(1) or decrement(0) OCD settings.
Table 153.
Memory controller parameters (continued)
Parameter
Description
