RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
135/844
priority of the associated command will be decremented by one (lower priority commands
are executed first). This increases the likelihood that this command will move to the top of
the command queue and be executed.
Note:
This command does not move relative positions in the command queue when it ages; the
new priority will be considered when placing new commands into the command queue.
Aging is controlled by a master aging-rate counter and command aging counters associated
with each command in the command queue. The age_count and command_age_count
parameters hold the initial values for each of these counters, respectively. When the master
counter counts down the age_count value, a signal is sent to the command aging counters
to decrement. When the command aging counters have completely decremented, the
priority of the associated command is decremented by one and the counter is reset.
Therefore, a command does not age by a priority level until the total elapsed cycles has
reached the product of the age_count and command_age_count values. The maximum
number of cycles that any command can wait in the command queue until reaching the top
priority level is the product of the age_count value, the command_age_count value, and the
number of priority levels in the system.
10.7
Low power operation
In many applications, it is highly desirable to minimize power consumption. The Memory
Controller provides various user configurable low power options to manage power savings.
In addition, a partial-array self-refresh option is included for mobile memory devices.
10.7.1
Low power modes
Five low power modes are available in the Memory Controller. The low power modes are
listed from least to most power saving.
Note:
It is not possible to exit one low power mode and enter another low power mode
simultaneously. The user should plan for a minimum delay between exit and entry between
the two low power modes of 15 cycles in which the Memory Controller must remain stable.
1.
Memory Power-Down
The Memory Controller sets the memory devices into power-down which reduces the
overall power consumption of the system. This is the low power modes having the least
effect: The Memory Controller and memory clocks are fully operational, but the CKE
input bit toward the memory devices is de-asserted.
The Memory Controller will continue to monitor memory refresh needs and will
automatically bring the memory out of power-down to perform these refreshes.
Whenever a refresh is required, the CKE bit will be turned enabled. This action drives
memory devices out power-down. Once the refresh has been completed, the memory
devices will be returned to power-down by de-asserting the CKE input bit.
2.
Memory Power-Down with Memory Clock Gating
The Memory Controller sets the memory devices into power-down and gates off the
clock to the memory devices. Refresh operations will be handled as seen above for the
Memory Power-Down mode (Mode 1), but the gating on the memory clock will be now
removed before asserting the CKE pin. After the refresh has been completed, the
memory devices will be returned to power-down with the clock gated. Before the
memory devices are removed from power-down, the clock will be gated on again.
Although this mode is supported in both mobile and non-mobile memory devices, clock
gating while in power-down is only allowed for mobile memory devices. Therefore, the
