RM0082
RS_SDIO controller
Doc ID 018672 Rev 1
689/844
Figure 74.
Data transaction sequence without DMA
Command Complete Int occur
Start
End
Clr Command Complete Status
Get Response Data
Wait for
Command Complete Int
Write or read ?
Wait for
Buffer Read Ready Int
Clr Buffer Read Ready Status
(1)
Set Command Reg
Set Block Size Reg
Set Block Count Reg
Set Argument Reg
Set Transfer Mode Reg
Get Block Data
Wait for
Buffer Write Ready Int
Clr Buffer Write Ready Status
Set Block Data
Wait for
Transfer Complete Int
Clr Transfer Complete Status
Abort Transaction
Infinite Block Transfer
Single or Multi
Block Transfer
Transfer Complete Int occur
Single/Multi/
Infinite Block
Transfer?
More Blocks?
More Blocks?
Buffer Read Ready occur
Buffer Write Ready
occur
Write
Read
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
No
No
Yes
Yes