RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
141/844
Reading the out-of-range parameters will trigger the Memory Controller to empty these
parameters and allow them to store out-of-range access information for future errors. The
interrupt should be acknowledged by setting bit 0 of the int_ack parameter to 1'b1, which will
in turn cause bit 0 of the int_status parameter to be cleared to 1'b0.
If a second out-of-range access occurs before the first out-of-range interrupt is
acknowledged, bit 1 of the int_status parameter will be set to 1'b1 to indicate that multiple
out-of-range accesses have occurred. If the out-of-range parameters have been read when
the second out-of-range error occurs, the details for this transaction will be stored in the out-
of-range parameters. If they have not been read, the details of the second error will be lost.
Even though the address has been identified as erroneous, the Memory Controller will still
process the READ or WRITE transaction. A READ transaction will return random data
which the user must receive to avoid stalling the Memory Controller. A WRITE transaction
will write the associated data to an unknown location in the memory array, potentially over-
writing other stored data. The command can not be aborted once accepted into the Memory
Controller.
10.8.2
Mobile devices DQS
For Mobile applications the user must add pull-down resistors on the DRAM boundary to the
DQS and DQS_n pins. These resistors enable the system to open the gate early without
receiving bad data. Both the resistors are very important and the system can not function
accurately without them.
10.8.3 Half
datapath
option
Memory Controller can also reduce the usable size of the bus between the Memory
Controller itself and memory devices. This feature is very useful when a different memory
part, having a smaller data width, is utilized. To use a memory device with a smaller
datapath, the half datapath option could be enabled setting the programmable reduce
parameter to 1'b1. The memory interface consists of the data signal (DQ) [15:0], data strobe
(DQS) [1:0] and data mask (DM) [1:0]. When the reduce parameter is set to 1'b1, only the
lower half of the memory interface is used. In this setting, the upper half bits of the
dm_disable, dqs_disable and data_disable signals are driven high, causing the upper half of
the data and data strobe buses to be driven low. The upper half of the data mask bus is
driven high.
If the reduce parameter is cleared to 1'b0, the Memory Controller will ignore the half
datapath option and work normally. In this case, the entire memory interface will be used.
displays the effect of the Half Datapath option on the memory interface buses.
Table 72.
Memory interface buses with Half Datapath option
Signal
Reduce parameter is set (1‘b1)
Reduce parameter is cleared(1‘b0)
Bus size
Relevant bit
Bus size
Relevant bit
Data DQ
[15:00]
[07:00]
[15:00]
[15:00]
Data DQS
[01:00]
[00:00]
[01:00]
[01:00]
Data DM
[01:00]
[00:00]
[01:00]
[01:00]
