RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
121/844
The Arbiter logic routes READ data from the Memory Controller core to the appropriate port.
The requesting port is assumed to be able to receive the data. WRITE data from each port
is connected directly to its own WRITE data interface inside the Memory Controller core,
allowing the ports to independently pass them to the Memory Controller core buffers.
10.5.1 Arbitration
overview
The weighted round-robin arbitration scheme is a three-step arbitration system. All
commands are routed into priority groups based on the priority of the requests. Inside each
priority group, requests are processed according to the “weight” (relative priority) of each
port. Finally, each priority group sends a single command to the priority select module,
which passes the highest priority command on to the Memory Controller core.
This arbitration scheme also supports two additional features. First, for situations where the
priority (port and relative) for multiple commands are identical, a port ordering system
whereby the user may adjust the order in which the ports are considered is provided.
Beside, for situations where two ports may be linked, a mechanism allowing the pair of ports
to share arbitration bandwidth for a better bandwidth efficiency, is also supplied.
Weighted round-robin arbitration is a complex arbitration scheme. To understand the
operation, each concept must be first understood individually. This will be matter of the
following Sections.
10.5.2 Understanding
round-robin operation
Round-robin operation is the simplest form of arbitration and is the best one for systems not
requiring requests to be treated preferentially to maintain bandwidth or minimize latency.
This scheme uses a counter that rotates through the port numbers, incrementing every time
a port request is granted.
If the port that the counter is checking has an active request and the Memory Controller core
command queue is not full, the request will be sent to the Memory Controller core.
If there is not an active request for that port, the port itself will be skipped and the next port
will be checked.
In any case, the counter is incremented one-by-one as any request has been processed,
regardless of which port's request was arbitrated.
Round-robin arbitration guarantees that each port's requests can be successfully arbitrated
into the Memory Controller core every N cycles, where N is the number of ports in the
component itself.
No port will ever be locked out, and any port can have its requests processed on every cycle
as long as all other ports are idle and the command queue is not full.
An example of the round-robin scheme is shown in
.
Cycles 0, 2 and 6 show the system behaviour when the command queue is full. Cycle 8
shows the system behaviour when the port addressed by the arbitration counter does not
have an active request.
All other cycles show normal behaviour.
