TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
word recognizer (WR) U120 (256 word x 4 bit RAM, HM10422) for trigger detection. These output lines are wired together
with U124 and U126 <2> (4-bit
binary
counter, F10016) outputs, respectively, to set up the WR.
During acquisition, the outputs of U124 and U126 are held at the reset level by the counter signal from U132 (quad TTL-
TO-ECL translator, 10124) which is generated by U130 (3-line to 8-line decoder/demultiplexer, 74LS 138) when the MPU
writes any data at I/O address 02
hex
.
During WR setup, all the M218’s outputs are set to off (low level) by the OFF/ON signal (TTL swing, shifted to -5V) from
U240A (quad comparator,
µ
PC339C) on the A02 INPUT-B board. This signal is delivered from U224 (hex D master-slave
flip-flop, 10176) on the A02 board when the MPU writes X1XXX
binary
serially at I/O address 01
hex
. This operation enables
U124 and U126 to act as a WR address counter to point to any address in the WR. This WR address counter can be
incremented by a clock pulse generated when the MPU writes to address 03
hex
.
The word written into the WR is provided along with signals EDBO, EDB1, and EDB2 from the A04 ACQ Memory board,
(translated from the TTL-level of the MPU data bus to ECL-level) The write pulse to the WR is generated by U130
(74LS138), and is converted to ECL-level by U132 (10124) when the MPU writes at I/O address 00
hex
.
For channels 8 through 15 on the A02 board, the operation is the same as that described in the preceding paragraph. The
words for WR U220 (HM10422) are supplied from EDB3, EDB4, and EDB5.
Each output of these two WRs is wired together on the A08 Mother board, and the outputs are sent to U136 and U138
(dual type D master-slave flip-flop, 10231) on the A03 ACQ Control board for triggering. These signals are routed to U146
(quad 2-input multiplexer/latch, 10173) on the A03 board. The data to U146 (10173) is latched by READ SQRAM from
U112 (binary to 1-8 line decoder, 10162) through inverter U126 (quad 2-input NOR gate, 10102), after being selected by
LDSQRAM from U108 (hex D master-slave flip-flop, 10176) on the A03 board. LDSQRAM is set when the MPU writes
X1XXXX
binary
at I/O address 51
hex
and READ SQRAM is generated by the MPU’s access to I/O address 5B
hex
.
The four outputs of U146 (10173) are connected to U142 (quad 2-input multiplexer, 10158) on the A04 board with the
outputs of the ACQ Memories U1 6 to U130 (HM10422) on the A04 board. Thus, all the ACQ Memories should be set to
off by forcing BS high. This is done by writing 1F
hex
into U114 (hex D master-slave flip-flop, 10176) on the A04 board with
WRITE BS from U112 (10162) on the A03 board.
The MPU reads the data from U152 (octal buffer/line driver with tri-state output, 74LS244) on the A04 board, when U152 is
enabled by OE from U112 (10162) via U126 (10102) on the A03 board. The data fed to U152 (74LS244) is selected by
U142 (10158) on the A04 board with the READ SQRAM signal from U112 (10162) on the A03 board at I/O address 59
hex
.
The data is translated from ECL to TTL level by U146 (quad ECL-TO-TTL translator, 10125) on the A04 board.
The MPU follows steps 1 through 4 of the I/O operation described in
Power
on paragraph at the begining of this test
section, and compares the data with the expected value for each I/O read. If the data is wrong, the MPU will issue an error
message.
7-15
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...