Tektronix 318, Technical Manual

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TM 11-6625-3145-14
Theory of Operation-318/338 Service
GLITCH CONTROL <2> <3> <4>
This circuit controls pin 15 of the M218s. M218’s pin 15 is used to control pin 14’s output. If pin 15 is forced high, glitch
trigger output pin 14 is disabled (kept low): if pin 15 is low, pin 14 is enabled. Therefore, if a glitch trigger on a certain line
is expected, the corresponding M218’s pin 15 must be low. Since all M218 pins 14 are wire-ORed, a glitch trigger occurs
when any of M218’s glitch trigger output moves to high. A01 U118 <2> and A02U218 <3> control M218’s pin 15; these
registers are written to serially; they output their data in parallel to their respective M218s. A02U240 <4> shifts the MPU
data and clock signals by --5 V, and shifts the TTL swing to match the M21 8’s special input level.
PIPELINE REGISTER <1> <3>
This circuit consists of latches A01U122, A01U128, and A01U134 <1>, and latches A02U228, A02U234, and A02U238
<3>. The sampled data and glitch from the M218s are applied to the inputs of the pipeline registers. The pipeline
registers synchronize the data for storage in the acquisition (ACQ) memory. Clock signals for the register are provided by
the SYSCLK 2 signal which is delayed by A01DL104 <2> (delayed SYSCLK 2 is called SYSCLK 3) and buffered by
A02U200C <4> . Each SYSCLK 2 pulse advances the data from the M218 to the register, where it is held for one clock
cycle before being loaded into the ACQ memory.
WORD RECOGNIZER <1> <2> <3>
The Word Recognizer (WR) consists of three 16-channel word recognizers with high-speed memories. The 318 offers
three word recognizer functions where three different words may be set simultaneously. They are named trigger words A,
B, and C. The MPU loads data into A01U120 <1 > and A02U220 <3>, according to the trigger word, using A01 U124 <2>,
A01 U126 <2>, A02U230 <3>, and A02U232 <3> (memory address counters). The MPU increments these counters one
by one and loads data for trigger word A, B, or C into A01 U120 and A02U220. Each WR RAM has 8 address lines and
three data lines. Data from the M218s is used as address for the WR RAM. Within the WR RAM, data is only three bits
wide, corresponding to triggers A. B, and C.
The MPU writes data, according to the trigger word, into the WR memory and increments the address counters. This
operation is repeated 256 times. For example, to set the trigger word 7638hex, the MPU writes 0 into the lower WR
memory where the address counter value is 38hex, and 0 is written to the higher WR where the counter value is 76hex. In
all the other addresses, the WR’s are filled with is.
During acquisition, data is supplied to A01U120 and A02U220 address inputs, and if a trigger word comes, A01U120 and
A02U220 (whose outputs are wired-ANDed) generate a trigger signal which is sent to the A03 Acquisition Control board.
DATA THRESHOLD BUFFER <4>
The currents from edge-connectors 38B and 39A are applied to the inverting inputs of A02U242B and A02U242A, (gain of
minus one) and the currents from A02J202 pins 4 and 5 and A02J204 are supplied to the non-inverting inputs of these
amplifiers to be summed. The input is divided down to 5/8 of the original value before it is sent to the non-inverting inputs
of A02U242A and A02U242B. The output current of these amplifiers is then supplied through A02R262 and A02R256 to
the parallel data probe.
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