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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Table 7-22
338 SQRAM TEST SQRAM DATA CONNECTIONS
Setup
SQRAM U144
Latch
MPU Data
DI0 (pin 6)
U106 Q1 (pin 3)
D0
DI1 (pin 7)
U106 Q3 (pin 13)
D1
DI2 (pin 18)
U108 Q1 (pin 3)
D2
DI3 (pin 19)
U108 Q3 (pin 13)
D3
To provide the data to the SQRAM, the MPU writes the two least significant bits of the four data bits into U106 (10176) at
I/O address 50
hex
, and the two most significant bits into U108 (10176) at I/O address 51
hex
.
Each address line of the SQRAM is connected to two output lines which are wired together as follows:
Table 7-23
338 SQRAM TEST SQRAM ADDRESS CONNECTIONS
Setup
SQRAM U144
TRIGGER F-F
Gate
MPU Data
A0 (pin 13)
U138 pin 15
U140 pin 2
D0
A1 (pin 14)
U150 pin 15
U140 pin 3
D1
A2 (pin 15)
U136 pin 15
U140 pin 4
D2
A3 (pin 16)
U136 pin 2
U140 pin 13
D3
A4 (pin 17)
U138 pin 2
U140 pin 14
D4
A5 (pin 9)
U150 pin 3
U140 pin 15
D5
A6 (pin 10)
U134 pin 2
U154 pin 14
D6
A7 (pin 11)
U148 pin 14
U154 pin 3
D7
In order to set up the SQRAM, the MPU data (translated to ECL-level) points to the address of the SQRAM. These data
bits are gated as in the table above, enabled by LDSQRAM from U108 <5> (10176) bit 4 on the A03 board. Bit 4 is
maintained high during this setup.
The write pulse to the SQRAM, WRITE SQRAM is generated when the MPU writes at I/O address 58
hex
. At the same
time, the address to the SQRAM is supplied by the MPU data.
The Read process is the same as in the WR Test, except that the inputs for U 146 (quad 2-input multiplexer/latch, 10173)
on the A03 board are switched to the outputs of the SQRAM.
During each read, the MPU verifies the data and issues an Error Message if it is not equal to the expected data.
7-115
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Page 532: ...TM 11 6625 3145 14 ...
Page 536: ...TM 11 6625 3145 14 ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Page 554: ......
Page 555: ...PIN 058584 ...