TM 11-6625-3145-14
Theory of Operation-318/338 Service
When the MPU reads the acquisition memory data, it sets the SELECT input (pin 9, READ ACQ DATA signal) to high, and
connects the acquisition memory data to the data selector output. If the SELECT input is low, acquisition status is
selected, and the MPU reads acquisition status as data.
ECL-to-TTL Translator and TTL Bus Buffer. The ECL-to-TTL translator and TTL bus buffer consists of A04U146,
A04U148, A04U150, A04U156, and A04U152. The ECL-to-TTL translator receives ECL-level signals from the data
selector A04U142 and A04U144. A04U146, A04U148, and A04U150 are ECL-to-TTL translators with totem-pole outputs.
A04U156 is a comparator with an open-collector output for wired-AND capability. The TTL bus buffer, A04U152, provides
the power booster with tri-state control for the I/O common bus. It is enabled by the RD and OE signals.
Full Valid Flag Latch. The full valid flag latch consists of A04U139B. It provides the Full Valid Data Display mode. This
latch is set by the SET F VALID signal and reset by the RESET signal from the A03 ACQ Control board.
LSI-B A04U140. The Sony/Tektronix A04U140 is a hybrid chip that provides simplified circuit construction, reduced circuit
board space, and lower power consumption. Its circuitry consists of an address decoder, divider, timer, and slow clock
detector.
The address decoder circuit consists of four decoders that enable the MPU to select the: sample interval, gate clock
interval, timer clock interval, and step clock . The address decoder provides necessary pulses for the initialization and
presetting of the above circuits. The selection is determined by the two bits of address and six bits of data from the MPU
when CS1X is low.
The divider circuit consists of a 7-stage decade counter, and divide-by-2 and divide-by-5 counters based on a ring counter
circuit. The output of these counters is delivered as the INTCLK signal via the 1-2-5 sequence selector.
The timer circuit consists of an output latch, which is reset by the RDSTS signal from the A03 ACQ Controlboard. It
generates a constant interval timing signal ranging from one to five multiples of the internally generated 100 ms clock.
The slow-clock detector circuit consists of two shift registers and a control flip-flop.
Figure 4-22. 338 Timing diagram of the slow-clock detector and timer circuit.
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Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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