Tektronix 318, Technical Manual

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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
In order to set up the SQRAM, the MPU data (translated to ECL level) points to the address of the SQRAM. These data
bits are gated as in the preceding table, enabled by LDSQRAM from U108 <5> (10176) bit 4 on the A03 board. Bit 4 is
maintained high during this setup.
The write pulse to the SQRAM, WRITE SQRAM, is generated when the MPU writes to I/O address 58
hex
. At the same
time, the address to the SQRAM is supplied by the MPU data.
The read process is the same as in the WR test, except that the inputs for U 146 (quad 2-input multiplexer/latch 10173) on
the A03 board are switched to the outputs of the SQRAM.
During each read, the MPU verifies the data and issues an error message if it is not equal to the expected data.
11. N & DELAY TEST
Program: N & DLY
Function:
Power on - The Event/Delay counter counts word "A" N times when functioning as the Event counter, and counts a certain
number of clock signals for delay when functioning as the Delay counter.
When functioning as the Event counter, the MPU loads a small N value into the counter register and increments the
counter using clock pulses while observing the carrry bit. The Delay counter functions the same way, using the DELAY
value as the initial counter value. In both cases the number of clock signals needed to generate the carry are compared
with the expected values.
Troubleshooting - This is not a verificaion test, so no test result will appear on the CRT screen. This test should be
observed on an oscilloscope. The troubleshooting routine automatically tests the N&DELAY Counter by alternately loading
and running the counter, first with N values as the Event counter, and then with DELAY values for the Delay counter. The
user programs the N and DELAY values before beginning the test. This test will run forever, or until the user presses the
STOP key. If no test values are entered, the N Counter is set to 1 and the DELAY counter is set to 0. In this case, the
N&DELAY Counter will not run. To run this test, N must be greater than 1, and DE-LAY must be greater than 0.
Description: Refer to Figure 7-10. The Event Delay Counter U158 (event/delay counter,
µ
PB3Z198R) on the A03 ACQ
CONTROL board is controlled by three signals, E, LOAD N, and LOAD DL from the SQRAM U144 (256 word X 4 bit RAM,
HM10422) on the A03 board. The counter generates N-1 as a carry when it reaches full count. This Event/Delay Counter
has two registers, the one which holds the N value is called the N-register and the one which holds the DELAY value is
called the DL register.
In this test, the MPU writes 000F
hex
as the N value into the N-register at I/O addresses 41
hex
and 42
hex
, and 005A
hex
as the
DELAY value into the DL register at I/O address 43
hex
and 44
hex
.
Start flip-flop U124B (dual type D master-slave flip-flip, 10131) on the A03 board is set by START2 from U110 (
binary
to 1-8
decoder/multiplexer, 10162) on the A03 board. U124B passes a clock signal generated by the MPU.
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