TM 11-6625-3145-14
Theory of Operation-318/338 Service
Table 4-1. (cont.)
318 LSI-A INPUT SIGNALS
Signal
Names
Description
TRIG’D
Active high; the output of the TRIG flag. It indicates that the Trigger sequencer is triggered.
RESET
Clears the flip-flop in LSI-A that temporarily saves the TRIG’D signal.
N
Active low; the output of the N flag. Indicates that NA in the Trigger sequence is completed.
STOP2
Active low; the output of the STOP flag. Indicates that data acquisition is complete.
CARRY
Active low; set by the carry flip-flop on the A04 board, which detects a car ry condition of the ACQ memory address
counter.
RDSTS
Generated at I/O address 5D
hex
by the MPU to request the status signals.
Table 4-2.
LSI-A OUTPUT SIGNALS
Signal
Names
Description
N-1
Active low; generated as a carry when the event/delay counter counts full.
INT
Active low; the output of INT flag in LSI-A. The MPU receives INT when an interrupt in the ACQ status logic occurs.
INT is caused by any change of any status signal, and the flag is reset by RDSTS.
WAFLG
Active low; read as NFLAG by the MPU issuing RDSTS. WAFLG is the output of the same latch which N is latched
into by the RDSTS signal.
DTFLG
Active high; read as TRIG’D FLAG by the MPU issuing RDSTS. DTFLG is the output of the same latch which
TRIG’D is latched into by the RDSTS signal.
STFLG
Active high; read as STOP FLAG by the MPU issuing RDSTS. STFLG is the output of the same latch which STOP2
is latched into by the RDSTS signal.
CAFLG
Active high; CARRY is read as CARRY FLAG by the MPU issuing RDSTS. CAFLG is the output of the same latch
which CARRY is latched into by RDSTS.
318 A04 ACQ MEMORY BOARD <8> <9>
ACQUISITION MEMORY AND ACO ADDRESS COUNTER <8>
The acquisition memory and ACQ address counter circuit consists of data memories for parallel acquisition and an
address counter for these memories. A simplified diagram of the acquisition memory and ACQ address counter is shown
in Figure 4-6.
Chip Select Latch. The chip select latch (A04U114) is used to enable each 8-bit pair of the acquisition memory and for
identifying instrument type. It is written by the MPU with the WRITE BS signal from the A03 ACQ Control board.
4-17
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Page 532: ...TM 11 6625 3145 14 ...
Page 536: ...TM 11 6625 3145 14 ...
Page 538: ...TM 11 6625 3145 14 ...
Page 539: ...TM 11 6625 3145 14 ...
Page 540: ...TM 11 6625 3145 14 ...
Page 541: ...TM 11 6625 3145 14 ...
Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Page 554: ......
Page 555: ...PIN 058584 ...