TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Table 7-7 318 SQRAM TEST PORT ADDRESSES (Hex)
Address
Content of Looping Test
5A
set CS all OFF into CS-latch to write 55 in the background of the SQRAM.
50
set 1 into QUAL (DO & D2) register and set 0 into QUAL (D1 & D3) register.
58
write 55 into the background of the SQRAM.
5B
SQRAM data is latched to read 55 from High-speed memory.
58
write AA into SQRAM after reading 55 from High-speed memory.
5B
SQRAM data is latched to read AA from High-speed memory.
When the ERROR looping function is selected, the program loops only if errors are detected. If no errors are detected, the
program runs once and displays the result of the verification just as if the looping function were turned OFF. If errors are
detected, the ERROR looping function is available for the read cycle of the test. The results of the read cycle verification
will appear on the screen. Refer to Appendix B of this manual for a description of error codes.
Description: Refer to Figure 7-9. The SQRAM U144 (256 word X 4-bit RAM, HM10422) on the A03 ACQ Control board
holds the trigger sequence table called Trigger menu.
The SQRAM receives data from U106 and U108 (hex D master-slave flip-flop, 10176) on the A03 board with the following
connection.
Table 7-8
318 SQRAM TEST SQRAM DATA CONNECTIONS
Setup
SQRAM U144
Latch
MPU Data
D10 (pin 6)
U106 Q1 (pin 3)
DO
DI1 (pin 7)
U106 Q3 (pin 13)
D1
D12 (pin 18)
U108 Q1 (pin 3)
D2
D13 (pin 19)
U108 Q3 (pin 13)
D3
To provide the data to the SQRAM, the MPU writes the two least significant bits of the four data bits into U106 (10176) at
I/O address 50
hex
, and the two most-significant bits into U108 (10176) at I/O address 51
hex
.
Each address line of the SQRAM is connected to two output lines which are wired together as follows:
7-21
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Page 532: ...TM 11 6625 3145 14 ...
Page 536: ...TM 11 6625 3145 14 ...
Page 538: ...TM 11 6625 3145 14 ...
Page 539: ...TM 11 6625 3145 14 ...
Page 540: ...TM 11 6625 3145 14 ...
Page 541: ...TM 11 6625 3145 14 ...
Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Page 554: ......
Page 555: ...PIN 058584 ...