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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
9.
ACQUISITION RAM TEST
Program: ACQ
Function:
Power on - All the ACQ RAMs are checked with the checkerboard marching pattern from 00 through FF.
Step 1. The word 55 is written into all RAM addresses.
Step 2. A word is read from a diagnostic cell and compared with the expected word 55.
If the diagnostic cell’s value is not equal to 55, an error message is displayed and the MPU is halted.
Step 3. If no error is found in the above test, the word AA is written into that cell. Then a word in same cell is read back
and is compared with AA. If that word is not equal to AA, an error message is displayed and the MPU is halted.
Step 4. Steps 2 and 3 are repeated for all RAM addresses.
Troubleshooting - This test is the same as that performed automatically when the power is turned on, but here the
Looping test feature is available. The Looping feature has four options; OFF, I/O, ERROR, and TEST. When the field is
set to I/O, the looping feature allows only I/O instrucions to be run repeatedly. The I/O address will appear on the screen.
When the field is set to ERROR, the looping feature allows the tests in which an error is detected to be run repeatedly.
When the field is set to TEST, the looping feature allows one test, or sequence of tests, to be run continuously. When the
field is set to OFF, the looping feature is not available and one test, or sequence of tests, runs once.
When the I/O Looping test is selected, only those OUT instructions (subroutines) including one of the addresses listed in
Table 7-6 below will run. Unless the STOP key is pressed, the selected portions of the test will loop continuously without
displaying the result of the verification. In this case, use an oscilloscope to observe the acquisition circuit board.
Table 7-6
318 ACQ TEST PORT ADDRESSES (Hex)
Address
Content of Looping Test
02
reset WR-address counter to increment WR-address counter to 55 to write 55 into
the background of High-speed memory.
5A
write CSO & CS1 into CS-latch to read 55 from High-speed memory.
55
write AA into High-speed memory after reading 55 from High-speed memory.
5A
write CSO & CS1 into CS-latch to read AA from High-speed memory.
55
write 55 into High-speed memory after reading AA from High-speed memory.
7-17
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...