TM 11-6625-3145-14
Theory of Operation-318/338 Service
The write enable (WE) Clock circuit consists of A03U132B, A03R1 12B, A03R132, and A03C106. The output of
A03U132B is wire-ORed with the output of the STOP flag and goes to the write enable inputs of the ACQ memory devices
on the A04 board <8>.
During data acquisition, data acquired from the parallel data probes is written into memory at the location pointed to by the
address counter. At the end of the data acquisition phase, the output of the STOP flag pulls the WE signal line high, and
data acquisition stops.
The width of the WE pulse is determined by adjustable capacitor A03C106.
The address clock (ADRSCLK) circuit consists of A03U132A, A03R112A, A03R134, and A03C104. The address clock
pulse generated by this circuit is applied to the clock inputs of address counter A04U136 and A04U138 on the A04 board
<8>.
During data acquisition, the address clock pulse, ADRSCLK, is routed to the address counter, which supplies the location
for the ACQ memory on the A04 board.
In the data read mode, the address clock is generated by STEP CLOCK.
The width of the address clock is determined by A03C104 <6>.
The trigger clock circuit consists of A03U130B, A03DL104A, A03DL104B, A03U142A, and A03U142B. The pulse
generated by the A03U130B and A03DL104B travels through A03DL104A to the trigger sequencer flags, at A03U150 and
A03U148, and LSI-A <7>. TRIGCLK1 goes to LSI-A; TRIGCLK2 goes to the trigger sequencer flags.
The trigger sequencer advances at the rate of the TRIG Clock as events are recognized.
NOTE
Refer to Figure 4-3 for a simplified block diagram of the ACQ control circuitry on
schematic <7>.
EXTERNAL OR GLITCH TRIGGER CIRCUIT <7>
The external or glitch trigger circuit consists of A03U122A, A03U122B, A03U124A, and A03DL1 06A.
The external trigger polarity is selected by gates A03U122A and A03U122B.
The polarity data EXT
↑
and EXT
↓
come from qualify register A03U106 <5>.
The external trigger signal selected is fed into the clock input of A03U124A. The glitch trigger is connected to the reset pin
and the TRIG QUAL signal is connected to the set pin.
Flip-flop A03U124A is enabled while TRIG QUAL is low. The output of EXTVG FLAG is connected to the input of one of
the retiming flip-flops (A03U138A).
RETIMING FLIP-FLOP <6>
The retiming flip-flops consist of A03U138A, A03U138B, A03U136A, A03U136B, and A03U134A.
The signals TRIG A, TRIG B, TRIG C, EXTVG FLAG, and TRIG QUAL are latched into each flip-flop by the retiming clock
(RETIMING CLK).
4-13
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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