TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
The write pulse to the WR U118 and U120 is generated by U1 12 (74LS138) and converted to ECL- level by U1114
(10124) at the time the MPU writes at I/O address 01
hex
. The I/O address to generate the write pulse for the U218 and
U122 is 00
hex
. Thus two of the four WRs are written at once; U118 and U120, or U218 and U122.
Each output of these four WRs are wired together on the A08 Mother board, and are sent to U136 and U 138 (dual type D
master-slave flip-flop, 10231) on the A03 ACQ Control board for triggering. In addition to that, these signals are routed to
U146 (quad 2-input multiplexer/latch, 10173) on the A03 board. The data to U146 (10173) are latched by READ SQRAM
from U112 (binary to 1-8 line decoder, 10162) through inverter U126 (quad 2-input NOR gate, 10102), after being selected
by LDSQRAM from U108 (hex D master-slave flip-flop, 10176) on the A03 board. LDSQRAM is set when the MPU writes
X1XXXX
binary
at I/O address 51
hex
, and READ SQRAM is generated by the MPU’s access to I/O address 5B
hex
.
The four outputs of U146 (10173) are connected to U142 (quad 2-input multiplexer, 10158) on the A04 board with the
outputs of the ACQ Memories U116 through U130 (HM10422) on the A04 board. Thus, all the ACQ Memories areset to
off by forcing BS high. This is done by writing 1F
hex
into U114 (hex D master-slave flip-flop, 10176) on the A04 board using
the WRITE BS signal from U112 (10162) on the A03 board.
The MPU reads the data from U152 (octal buffer/line driver with tri-state output, 74LS244) on the A04 board when enabled
by OE from U112 (10162) via U126 (10102) on the A03 board. The data fed to U152 (74LS244) are selected by U142
(10158) on the A04 board with READ SQRAM from U1 12 (10162) on the A03 board at I/O address 59
hex
, and are
translated from ECL-to-TTL by U146 (quad ECL-to-TTL translator, 10125) on the A04 board.
The MPU follows Steps 1 through 4 of the I/O operation described in the preceding
Power On
para- graph, and compares
the data with the expected value on each I/O read. If the data is incorrect, the MPU will issue an error message.
7-108
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...