Tektronix 318, Technical Manual

Page: 264 / 555

TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
PARALLEL ANALYZER
7. CLOCK TEST
Program: CLK
Function
Power on - The timebase is programmed for several ranges; its operation is checked by the MPU, which monitors the
slow clock flag on each timer interrupt.
Troubleshooting - This is not a verification test, but the user should observe the timebase with an oscilloscope or some
similar instrument. ALL (all programmable timebases) or SINGLE (one particular timebase) can be selected from the
menu for this test.
If ALL is selected, each of the possible timebase values is sequentially set up into the timebase and tested for
approximately five seconds. The next timebase value is then loaded. This test will run continuously until the STOP key is
pressed. The CRT screen will display the timebase range being set up. If SINGLE is selected, the user enters the range
to be observed using the keyboard and then presses the START key. In this case, nothing will appear on the screen.
The following programmable timebase ranges are available:
20nS, 50nS, 100nS, 200nS, 500nS, 1
µ
S, 100uS, 1mS, 10mS, 1S
Description: Refer to Figure 7-6. The Slow Clock Detector compares the SYSCLK signal coming into this detector with
the gate clock internally selected. As long as the SYSCLK is two or more times as fast as the gate clock the slow clock
flag is not set. If the SYSCLK is less than twice as fast as the gate clock the slow clock flag is set.
This program also checks the clock path using the Slow Clock Detector.
The MPU selects the internal CLK by writing 111110
binary
into shift register U224 (hex D master- slave flip-flop, 10176) on
the A02 INPUT-B board at I/O address 01
hex
. This shift register enables U222B (dual 3-input 3-output NOR gate, 10211)
on the A02 board which transmits the INTCLK signal.
The Slow Clock Detector, the Timer, and their associated circuits are located in U140 (timebase,
µ
PB3Z1 99R) on the A04
ACQ Memory board. The Timer is programmed to generate an interrupt to the MPU every 100 ms. Then the MPU
unmasks the Timer Interrupt and sets the gate clock and the SYSCLK interval as shown in Table 7-4.
7-11