Tektronix 318, Technical Manual

Page: 77 / 555

TM 11-6625-3145-14
Theory of Operation-318/338 Service
N Register. The N register is a 16-bit register that holds the N value assigned in the Trigger menu. The MPU writes the N
value into the N register at I/O addresses 41
hex
and 42
hex
.
DL Register. The DL register is a 16-bit register that holds the DELAY value assigned in the Trigger menu. The MPU
writes the DELAY value into the DL register at I/O addresses 43
hex
and 44
hex
.
Mask Register. The Mask register is a 5-bit register that holds mask bits for interrupts. The MPU writes the mask data
into the mask register at I/O address 40
hex
.
Event/Delay Counter. The event/delay counter is a 16-bit synchronous preloadable counter with fast-carry propagation
logic.
The counter is controlled by three signals: CE, LOADN, and LOADDL which are described in Table 4-A. The counter
includes carry detection Logic which generates the N-1 signal when it counts out.
ACQ Status Logic. The ACQ status consists of four flags (DTFLG, WAFLG, STFLG, and CRFLG) and the INT signal.
The MPU gets these signals (except INT ) by issuing RDSTS at I/O address 5D
hex
.
INT is caused by any state change of any flag, and each flag bit can be masked by the mask bit of the mask register.
The function of each signal in LSI-A is shown in Table 4-1.
Table 4-1.
318 LSI-A INPUT SIGNALS
Signal
Names Description
EN Active low; indicates that the MPU provides data on the data bus (DO-D7) to LSI-A.
CSox Active low; indicates that the MPU accesses the LSI-A.
AO-A2 The data for the address decoder located in the LSI-A.
DO-D7 The data bus. The MPU puts data for LSI-A on the bus.
TRIG CLK Active high; connected to the clock input of the event/delay counter. The counter increments or loads the contents
of the N register or the DL register according to the control signals.
CE Active low; the count enable signal. The counter increments at the rising edge of TRIG CLK if CE is low.
LOADN Active high; if high, the N value of the N register is loaded into the counter at the rising edge of TRIG CLK.
LOADDL Active high; if high, the DELAY value of the DL register is loaded into the counter at the rising edge of the TRIG CLK.
TIMER Timer from LSI-B (A04U140 <9>) occurs at a constant interval after it is cleared by the CLR INT signal at I/O address
5F
hex
.
4-16