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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Description - The NVM address is from EOOO through E7FF; NVM address select signal (NVMCS) is supplied from the
address decoder on the MPU (A06) board through bus connector 46B. The NVM chip is selected by the inverse NVMCS
and the power(+5V) monitor signal. If the power monitor circuit detects low power (< 4.6V), the NVM can not be selected.
NVM data is gated by U25, which is controlled by the BRD, BIORQ, and NVMCS signals. The RD and WR signals (these
are inverse signals of BRD and BWR) control the direction of NVM data.
16.
RS-232 TEST
Program: TSTRM1 (power on), TSTRM2 (Troubleshooting)
Setup: - Before starting TSTRM2, you must connect the self test adapter to the RS-232 communication port. (Refer to
Figure 7-23.)
Function:
Power on - TSTRM1 initializes the SIO Port-B and reads its initial status. If the initial status is good, it loads dummy data
into the SIO and checks for status change.
Troubleshooting - TSTRM2 diagnostic has the following three functions;
1.
checks MODEM control signals
2.
checks the SIO Port-B status
3.
checks data transmit and receive functions
Function 1 includes eight test programs. These programs check the status of MODEM signals RTS, CTS, CD, DTR, and
DSR.
Function 2 includes seven test programs. These programs check the SIO Port-B initial status.
Function 3 includes nine test programs. These programs transmit increment pattern data from SIO Port-B, then receive
and compare that data against the original data. Data speed is changed automatically from 110 baud through 9600 baud.
(Test data format is fixed at 8 bits/word, even parity, and one stop bit, )
Description - Refer to the 01 Option I/O function list, and simplified block diagrams for SERIAL and RS-232 when reading
the following.
The SIO and other option hardware I/O address is decoded by U30. The SIO Port-B cotrolls RS- 232 functions; that
address is 92 and 93, and the RS-232 baud rate selector address is 88.
The SIO data line is common for both Port-A and Port-B. These eight data lines connect to buffer U25; U25 is gated by
the option I/O address.
The SIO timing is synchronized by the CPU clock. That clock is supplied from the MPU on the A06 board through bus
connector 31A, and its waveform is adjusted by U12 and U32 before reaching the SIO.
All but one of the MODEM control signals are controled by SIO Port-B. The exception is the DSR signal, which appears in
the option status register at address 80. All the signals coming into Port-B are converted from RS-232 levels to TTL levels
by the receiver, U40; and all outgoing signals are converted from TTL levels to RS-232 levels by the transmitter, U41.
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Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...