TM 11-6625-3145-14
LIST OF ILLUSTRATIONS
Figure
Page
Failure in the power-up Self Test .................................................................................................................. 3-6
Successful completion of the power-up Self Test ......................................................................................... 3-6
Diagnostics menu: first display...................................................................................................................... 3-7
Display sample with ALL/SINGLE and data entry fields................................................................................ 3-7
Display sample with LOOP and DISP fields.................................................................................................. 3-7
Display for KBD tests..................................................................................................................................... 3-8
CRT test: first display .................................................................................................................................... 3-8
CRT test: second display .............................................................................................................................. 3-9
CRT test: third display ................................................................................................................................... 3-9
CRT test: fourth display................................................................................................................................. 3-9
Display for CLK tests..................................................................................................................................... 3-10
Display for word recognizer’s RAM tests....................................................................................................... 3-10
Display for acquisition’s RAM tests ............................................................................................................... 3-11
Display for trigger sequencer’s RAM tests .................................................................................................... 3-11
Display for N counter or DLY counter tests ................................................................................................... 3-12
Display for overall tests on parallel acquisition.............................................................................................. 3-12
Display for threshold tests ............................................................................................................................. 3-13
Setup of probe compensation ....................................................................................................................... 3-13
Display for probe compensation.................................................................................................................... 3-14
Setup for serial tests...................................................................................................................................... 3-15
Display for serial tests ................................................................................................................................... 3-15
Setup for remote tests ................................................................................................................................... 3-16
Display for remote tests................................................................................................................................. 3-16
Display for non-volatile memory tests ........................................................................................................... 3-17
318 Input A and Input B block diagram ......................................................................................................... 4-8
318 Simplified diagram of the ACQ control circuitry on schematics <5> and <6> ........................................ 4-9
318 Simplified diagram of the ACQ control circuitry on schematic <7> ........................................................ 4-10
318 SQRAM data register format .................................................................................................................. 4-11
318 Qualify register format ............................................................................................................................ 4-11
318 Simplified diagram of the acquisition memory and ACQ address counter circuit .................................. 4-18
318 Simplified diagram of the timebase and MPU bus interface circuit ........................................................ 4-23
318 Timing diagram of the slow-clock detector and timer circuit .................................................................. 4-24
318/338 Simplified diagram of the ROM and threshold circuits .................................................................... 4-26
318/338 Simplified diagram of the MPU/Display board................................................................................. 4-29
318/338 Simplified diagram of the serial acquisition and RS-232C circuit.................................................... 4-31
318/338 Simplified diagram of the CRT circuit .............................................................................................. 4-35
318/338 Simplified diagram and waveform of the horizontal sweep generator............................................. 4-36
318/338 Simplified diagram of the power supply circuit ................................................................................ 4-38
338 Input A and Input B block diagram ......................................................................................................... 4-41
338 Simplified diagram of the ACQ control circuitry on schematics <5> and <6> ........................................ 4-43
338 Simplified diagram of the ACQ control circuity on schematic <7> ......................................................... 4-44
338 SQRAM data register format .................................................................................................................. 4-45
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Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...