TM 11-6625-3145-14
Theory of Operation-318/338 Service
TRIG A, TRIG B, and TRIG C are issued from the word recognizer on the A01 and the A02 boards.
The outputs of these flip-flops are wire-ORed with the outputs of the address buffer (A03U140, A03U154B, and
A03U154C) and go to the address inputs of the SQRAM (A03U144).
ADDRESS BUFFER <7>
The address buffer consists of A03U140, A03U154 B, and A03U154C. These gates can be enabled only while setting up
the SQRAM (A03U144). Their outputs are used as the address to the SQRAM when loading the trigger sequence table.
See Trigger Sequencer RAM, following.
The control signal of the gates comes from A03U108 <5> and is called LDSQRAM.
TRIGGER SEQUENCER RAM <7>
The trigger sequencer RAM (SORAM) is a 4-bit high-speed memory consisting of A03U144.
The memory can be operated in either read or write mode. Before acquisition, the memory is operated in write mode.
During acquisition, the SQRAM is operated in read mode.
To provide a trigger sequencer table to the SQRAM, the MPU writes the data already set in data registers (A03U106 and
A03U108 <5>) into the SQRAM at I/O address 58
hex
. The address to the SQRAM is supplied by the MPU data.
The memory address is determined by the current status of the retiming flip-flops. The data from the SQRAM is applied to
the trigger sequencer flags.
The data consists of four signals: CE , LOADL, LOADDN, and SUCCEED.
The signal CE enables the event delay counter in the LSI-A.
The LOADN signal indicates that the contents of the N register (which holds the N value in LSI-A) are loaded into the
event,/’delay counter at the ’rising edge of the trigger clock.
The LOADDL signal indicates that the contents of the DL register (which holds the delay value in LSI-A) is loaded into the
event delay counter by the trigger clock.
The SUCCEED signal is used when the trigger sequence is in the succeed mode. The trigger words must be satisfied
sequentially in order to generate the trigger.
TRIGGER SEQUENCER FLAG <7>
The trigger sequencer flag circuit consists of A03U150A, A03U150B, A03U148B, A03U148A, A03U152A, A03U152B,
A03U156C, A03U154A, A03U1566B, A03U154D, A03U156A, A03U156D, and A03U122C.
It contains four main flags: N flag, TRIG’D flag. SUCCEED flag, and STOP flag.
N Flag Circuit. The N flag circuit consists of A03U150B, A03U152B, and A03U152A.
The output of the carry flag of the event/delay Counter In LSI-A N-1 goes to low when word A has been counted N-1 times.
This bit is applied to the inputs of the N flag flip-flop (A03U150B).
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Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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