TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
ROM7 enables the read operation of the Jump Table ROM. It is generated by U005 (dual 2-line to 4-line
decoder/demultiplexer, 74LS139). U001 (74LS139) on the A05 board decodes the BM1, BMREQ, and AB11 through
AB15 signals.
The MPU reads the output data from the Jump Table ROM U026 through U045 (octal bus transceiver with tri-state output,
74LS245) and through the A08 board.
The MPU calculates the checksum with all the data contained in the Jump Table ROM, and compares it with the expected
value, also stored in this ROM. If the values do not match the MPU issues an error message.
4.
DISPLAY RAM TEST
Program:
Function:
Power on The Display RAM is checked with a checkerboard marching pattern from E800 to EFFF. (A checkerboard
marching pattern is an alternating 0 and 1 pattern that is loaded into a memory location, checked, shifted, and checked
again.)
Step 1. The word 55 is written into all RAM addresses.
Step 2. A word is read from a diagnostic cell and compared with the expected word 55. If it is not equal to 55, an error
message is displayed and the MPU is halted.
Step 3. If the previous test is successfully completed, the word AA is written into that cell. Then a word in the same cell is
read back and is compared with AA. If it is not equal to AA, an error message is displayed and the MPU is halted.
Step 4. Steps 2 and 3 are repeated for all RAM addresses.
Troubleshooting - None.
Description: The read and write operation on the Display RAM U515 (16 K-bit static CMOS RAM, uPD446/HM6116P) on
the A06 MPU/Display board is completely controlled by Display Controller U500 (Display Controller, MB62110) on the A06
board.
The MPU reads/writes data from/to the Display RAM through U525 (octal bus transceiver, 40H245) on the A06 board,
which is enabled by the Display Controller and has the data direction specified (read or write) by the MPU’s read signal.
The addresses to the Display RAM are supplied by both the MPU and the Display Controller, however the addresses from
the MPU are sent to the Display Controller and the Display Controller gates these signals to the Display RAM.
If there is competition between the MPU and the Display Controller for access to the Display RAM, the Display Controller
forces the MPU to wait until it completes the current read operation by asserting the WAIT signal to the MPU.
The MPU checks the Display RAM with the checkerboard marching pattern. The read and write sequences have already
been mentioned in the
Power on
paragraph at the begining of this section. If the data read is incorrect, the MPU will issue
an error message.
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Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...