TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
PARALLEL ANALYZER
7.
CLOCK TEST
Program: CLK
Function:
Power on - The timebase is programmed for several ranges; its operation is checked by the MPU, which monitors the
slow clock flag on each timer interrupt.
Troubleshooting - This is not a verification test, but the user should observe the timebase with an oscilloscope or some
similar instrument. ALL (all programable timebases) or SINGLE (one particular timebase) can be selected from the menu
for this test.
If ALL is selected, each of the possible timebase values is sequentially set up into the timebase and tested for
approximately 5 seconds, and then the next timebase value is loaded. This test will run continuously until the STOP key is
pressed. The CRT screen will display the timebase range being set up. If SINGLE is selected, the user enters the range
to be observed using the keyboard and then presses the START key. In this case, nothing will appear on the screen.
The following programmable time base ranges are available:
20 ns, 50 ns, 100 ns, 200 ns, 500 ns, 1
µ
s, 100 us, 1 ms, 10 ms, 1 s
Description: Refer to Figure 7-38. The Slow Clock Detector compares the SYSCLK signal coming into this detector with
the gate clock internally selected. As long as the SYSCLK is two or more times as fast as the gate clock the slow clock
flag is not set. If the SYSCLK is less than twice as fast as the gate clock the slow clock flag is set.
This program also checks the clock path using the Slow Clock Detector.
The MPU selects the internal CLK by writing 11110
binary
into shift register U224 (hex D master- slave flip-flop, 10176) on
the A02 INPUT-B board at I/O address 01
hex
. This shift register enables U222B (dual 3-input 3-output NOR gate, 10211)
on the A02 board which transmits the INTCLK signal.
The Slow Clock Detector, the Timer, and their associated circuits are located in U140 (timebase, APB3Z1 99R) on the A04
ACQ Memory board. The Timer is programmed to generate an interrupt to the MPU every 100 mS. The MPU then
unmasks the Timer Interrupt and sets the gate clock and the SYSCLK interval as shown in Table 7-18.
The INTCLK signal is generated by the timebase circuit, U140, which counts 10 ns clock pulses to produce a range of time
base signals ranging from 20 ns through 500 ms. The INTCLK signal is buffered by U112 (quad 2-input NOR gate,
MC1662) on the A04 board. This signal is sent to U222 on the A02 board through the A08 Mother board. The output of
U222 is returned to the SYSCLK in-put of U140 on the A04 board via the A08 board.
U158 (event/delay counter,
µ
PD3Z198R) on the A03 ACQ Control board generates the interrupt to the MPU when it
receives the Timer signal from U140 on the A04 board. This interrupt is sent to the MPU as INT via U156 (comparator
with open collector output, #PD31 1 C) and via the A08 board.
The MPU reads the status by issuing READ STATUS at I/O address 5D
hex
through U152 (octal buffer/line driver with tri-
state output, 74LS244). U 152 is enabled by OE from U 126 (quad 2-input NOR
7-104
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
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Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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Page 555: ...PIN 058584 ...