Tektronix 318, Technical Manual

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TM 11-6625-3145-14
Theory of Operation-318/338 Service
ACQ Address Counter and Carry Latch. The ACQ address counter designates the memory location for each data bit to
be stored. The counter, consisting of A04U136 and A04U138, is a synchronous, 8-bit (divide by 256) binary counter which
is reset to zero by the RESET signal from the A03 ACQ control board at the beginning of each acquisition.
The counter outputs Q0 through Q3 are connected to the address inputs of A04U116, A04U118, A04U120, A04U122,
A04U124, A04U126, A04U128, A04U130, A04U132, and A04U134.
Counter A04U138 provides a carry output to the carry latch, A04U139A. After one full memory cycle, the carry latch
provides a latched low-level signal on the pin 2 output of A04U139A. It serves as the address counter CARRY signal.
TIMEBASE AND MPU BUS INTERFACE <9>
The timebase and MPU bus interface circuit consists of the frequency divider, timer, slow clock detector, INTCLK buffer,
data selector, full valid flag latch, TTL-to-ECL translater, ECL-to-TTL translator, and the address decoder. A simplified
diagram of this circuit is shown in Figure 4-21.
TTL-to-ECL Translator. The TTL-to-ECL translator consists of A04U100, A04U102, A04U104, A04U106, and A04U108.
It accepts a TTL-level signal from the MPU bus and translates it to a differential ECL-level signal.
Address Decoder. The address decoder consists of A04U112C and A04U110. It provides the chip-select and enable
signals which select the specific device needed to communicate with the MPU. This selection is determined by outputs
from the 3-line-to-8-line decoder, A04U110. Gate A04U112C supplies the I/O enable signal EN (which is an ORed signal
of BRD and BWR).
Oscillator. The oscillator circuit consists of A04U112A and A04U112B <9>. A04U112A and crystal A04Y100 form a 100
MHz crystal-controlled oscillator. The 100 MHz oscillator is buffered by A04U112B before being divided by A04U140
(LSI-B).
Divider, Timer, and Slow Clock Detector. The divider, timer, and slow clock detector are contained on (LSI-B)
A04U140. More information about LSI-B is provided under the paragraph labeled
LSI-B (A04U140) .
The frequency divider provides the 20 ns to 500 ms clock output. A clock output is determined by the internal timebase
selection register. The selected internal clock signal is sent to the INTCLK buffer A04U112D. The INTCLK selection data
is shown in Table 4-15.
The timer generates the selected constant interval signal for an interrupt to the MPU. This signal is reset by the RDSTS
signal.
The slow-clock detector circuit provides the capability to detect a slow sampling clock rate (clock less than 25 ms) in the
external clock operation mode. When the clock rate is slow, the CLKSLW signal holds a high state and the MPU displays
SLOW CLOCK on the screen. The timing diagram of the timer and the slow-clock detector circuit is shown in Figure 4-22.
INTCLK Buffer. The INTCLK buffer consists of A04U112D. It provides a power boost and improves the waveform shape
for INTCLK signals on the bus.
Data Selector. The data selector consists of A04U142 and A04U144. It provides data selection of either acquisition
memory output or acquisition status output. This data selector is controlled by the READ ACQ DATA signal.
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