TM 11-6625-3145-14
Theory of Operation-318/338 Service
SERIAL DATA ACQUISITION <18>
The serial data acquisition circuit consists of the data bus buffer, I/O selector, baud rate selector, external trigger latch, and
serial I/O controller. It provides the serial data acquisition function. A simplified iagram is shown in Figure 4-11.
Data Bus Buffer. Bidirectional bus transceiver A07U25, with tri-state outputs, serves as the data bus buffer, allowing data
transmission either from the A-side bus to the B-side bus or from the B-side bus to the A-side bus of the buffer. The logic
level on the BRD line controls the direction of data transmission, and the I/O ENABLE line either enables or isolates the
entire transceiver.
The I/O ENABLE line is enabled when I/O addresses 80 through 9F
hex
, or the NVMCS (Non-volatile Memory Chip Select),
are asserted. These two conditions are selected by A07U21A and A07U13.
Table 4-8.
DATA BUS BUFFER CONTROL
I/O Enable
RD
Data Transmission
Low
Low
B side to A side
Low
High
A side to B side
High
X (don’t care)
Isolated
I/O Selector. The I/O selector A07U30 allows the MPU to address five I/O devices. A07U30 is enabled when the bus
BM1 signal is false (low), the BWR or BRD signal is true (low), and I/O addresses 80 through 93
hex
are selected.
The output of A07U30 is controlled by bus lines A4, A3, and A2, supplied to pins 3, 2, and 1, respectively.
The functions and addresses of selected I/O operations are shown in Table 4-9.
Baud-Rate Selector. The baud-rate selector circuit consists of a programmable bit rate generator (A07U6), and bus data
latches A07U31 and A07U22A. The programmable bit-rate generator A07U6 supplies the receiver clock signal to the
SlO’s PORT-A. The output clock rate of its pin 10 is determined by the logic input at its pins 11, 12, 13, and 14 (S3
through S0, respectively).
The output positive-going edge at pin 12 of I/O selector A07U30 allows A07U31 and A07U22A to latch data. That latched
data (D7, D6, D5, and D4) output is applied to inputs S3-S0 of A07U6.
Latched data from D4 has another function. It selects the clock used as input at pin 15 of A07U6 (either 19.2K baud or the
external clock). The chip select function operates when S1, S2, and S3 are low The clock select signal at A07U6 pin 15 is
called IM. Inverter A07U20A inverts and shapes the baud-rate clock. Table 4-10 shows the 16 input combinations and the
corresponding output rates.
4-32
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
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Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
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Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
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Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
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