TM 11-6625-3145-14
Theory of Operation-318/338 Service
The CLKSLW signal is initialized to high level by the RDSTS signal.
If the SYSCLK signal is either high or low for two or more consecutive pulses, the internal shift registers are not clocked,
and the low level at the input of the first shift register bit is not transferred to the second shift register; this causes the
CLKSLW signal to be output.
When the SYSCLK is less than 25 ms (slow rate), the shift registers are clocked by SYSCLK. But the CLKSLW output is
not changed because a control gate of the shift register closes before the second rising edge of SYSCLK arrives.
When the SYSCLK rate is fast (above 25 ms), the low level pulse provided by the first shift register is successfully
transferred to the second shift register which cancels the CLKSLW output.
The four conditions of the CLKSLW output (high, slow, low, and fast) must be read before the start of gate timing, because
the CLKSLW signal is changed by the gated SYSCLK.
The function of each signal in A04U140 is as follows:
Table 4-13.
318 LSI-B (A04U140) INPUT SIGNALS
Signal
Names
Description
EN
Generates data latch strobe. The data latch state is changed by a low-level pulse of this signal.
CS1X
Chip select for A04U140.
A1-A0
Address for data latch. (A1=MSB, A0=LSB)
D5-D0
Data for internal selector. (D5= MSB, D0= LSB)
10NCLK
10 ns clock for internal d ivider.
SYSCLK
System clock to be compared with gate clock in the Slow Clock Detector circuit.
RDSTS
Read status for Slow Clock Detector circuit operations; trigger and timer output are reset.
Table 4-14
318 LSI-B (A04U140) OUTPUT SIGNALS
Signal
Names
Description
INTCLK
Selected internal clock (20 ns - 500 ms).
10UCLK
10 us period clock for the test output on the A01 board.
CLKSLW
Compared result of slow clock detector circuit. This signal condition is:
0 - One period of SYSCLK is shorter than a hal f interval of gate clock.
1 - One period of SYS(CLK is longer than a half interval of gate clock.
TIMER
Constant interval timer with reset by RDSTS.
4-56
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Page 532: ...TM 11 6625 3145 14 ...
Page 536: ...TM 11 6625 3145 14 ...
Page 538: ...TM 11 6625 3145 14 ...
Page 539: ...TM 11 6625 3145 14 ...
Page 540: ...TM 11 6625 3145 14 ...
Page 541: ...TM 11 6625 3145 14 ...
Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Page 554: ......
Page 555: ...PIN 058584 ...