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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
Table 7-10
318 THRESHOLD TEST DATA VALUES
V1
V2
V3
Expected
+0.3V (83
hex
)
-0.1V (7F
hex
)
+0.2V
1
+0.7V (87
hex
)
-0.5V (7B
hex
)
+0.2V
1
+1.1V (8B
hex
)
-0.9V (77
hex
)
+0.2V
1
+ 1.9V (93
hex
)
- 1.7V (6F
hex
)
+0.2V
1
+ 3.5V (A3
hex
)
-3.3V (5F
hex
)
+ 0.2V
1
+ 6.7V (C3
hex
)
-6.5V (3F
hex
)
+ 0.2V
1
-0.3V (7D
hex
)
+ 0.1V (81
hex
)
-0.2V
0
-0.7V (79
hex
)
+ 0.5V (85
hex
)
-0.2V
0
-1.1V (75
hex
)
+0.9V (89
hex
)
-0.2V
0
-1.9V (6D
hex
)
+1.7V (91
hex
)
-0.2V
0
-3.5V (5D
hex
)
+3.3V (A1
hex
)
-0.2V
0
-6.7V (3D
hex
)
+6.5V (C1
hex
)
-0.2V
0
V3 is calculated by (V1 +V2)/2 using two resisters, R1 10 and R1 15 (4.99 KQ) on the A05 baord. V3 is selected by U114
(differential 4-channel multiplexer, 4052BP) on the A04 board and sent to U236 (ultra fast dual comparator, SP9687) and
the Comparator U240C (quad comparator,
µ
PC339C) on the A02 INPUT-B board through the A08 board. In the A02
board, V3 is compared with ground by the U240C Comparator and this result is sent to 244C (quad 2-inputNOR gate,
10102) on the A02 board. U244C is enabled by U224 (hex D master-slave flip-flop, 10176) on the A02 board when the
MPU writes 0XXXX
binary
into it at I/O address 01
hex
. U244C (10102) on the A02 board outputs the Threshold TEST signal
to U144 (quad 2-input multiplexer, 10158) on the A04 board via the A08 board.
During this test, all outputs of the ACQ Memories on the A04 board are disabled (maintained at a low level) by forcing BS
to high from U114 (hex D master-slave flip-flop, 10176) on the A04 board. U114 is written by the MPU at I/O address
5A
hex
.
The MPU reads the data from the A04 board at I/O address 59
hex
, i.e., with READ ACQ DATA from U112 (binary to 1-8
decoder/multiplexer, 10162) on the A03 board. This reading sequence is the same as in the ACQ Test.
Then the MPU compares the MSB of the data read with the one expected. If they don’t match each other, the error
message will be issued.
7-27
Summary of Contents for 318
Page 119: ...318 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 182: ...338 VERIFICATION AND ADJUSTMENT PROCEDURES ...
Page 253: ...318 ___________________ TROUBLESHOOTING TREES ...
Page 344: ...338 TROUBLESHOOTING TREES ...
Page 517: ...TM 11 6625 3145 14 318 338 4434 923 318 Block Diagram ...
Page 518: ...TM 11 6625 3145 14 318 338 4434 924 338 Block Diagram ...
Page 519: ...TM 11 6625 3145 14 318 338 4434 925 318 Acquisition Module Wiring Diagram ...
Page 520: ...TM 11 6625 3145 14 318 338 4434 926 318 338 Mainframe Wiring Diagram ...
Page 521: ...TM 11 6625 3145 14 318 338 4434 926 338 Acquisition Module Wiring Diagram ...
Page 522: ...TM 11 6625 3145 14 318 338 4434 928 Figure 9 1 318 A01 Input A Board Component Locations ...
Page 526: ...TM 11 6625 3145 14 ...
Page 528: ...TM 11 6625 3145 14 Figure 9 3 318 338 A03 ACQ Control Board Component Locations ...
Page 532: ...TM 11 6625 3145 14 ...
Page 536: ...TM 11 6625 3145 14 ...
Page 538: ...TM 11 6625 3145 14 ...
Page 539: ...TM 11 6625 3145 14 ...
Page 540: ...TM 11 6625 3145 14 ...
Page 541: ...TM 11 6625 3145 14 ...
Page 542: ...TM 11 6625 3145 14 Figure 9 8 318 338 A10 CRT Board Component Locations ...
Page 544: ...TM 11 6625 3145 14 Figure 9 9 318 338 A11 Inverter Board component Locations ...
Page 546: ...TM 11 6625 3145 14 Figure 9 10 318 338 A12 Regulator Board Component Locations ...
Page 551: ...TM 11 6625 3145 14 Figure 9 12 338 A01 Input A Board Component Locations ...
Page 553: ...TM 11 6625 3145 14 318 338 SERVICE ...
Page 554: ......
Page 555: ...PIN 058584 ...