Rev. 5.00, 12/03, page 172 of 1088
T
1
Address bus
φ
CS0
AS
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower address changed
Read data
Read data Read data
Figure 6-15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.5.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the
WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
Summary of Contents for H8S/2318 series
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