Renesas H8S/2318 series, Hardware Manual

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Rev. 5.00, 12/03, page 419 of 1088
Address
φ
Internal write signal
TCNT input clock
TCNT
N M
T
1
T
2
TCNT write cycle
Counter write data
Figure 11-8 Contention between TCNT Write and Increment
11.5.2 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the
incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors may occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.