Renesas H8S/2318 series, Hardware Manual

Page: 402 / 1121

Rev. 5.00, 12/03, page 372 of 1088
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9-46 shows the timing
for status flag clearing by the CPU, and figure 9-47 shows the timing for status flag clearing by the
DTC.
Status flag
Write signal
Address
φ
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
Figure 9-46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
φ
Source address
DTC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC
write cycle
Figure 9-47 Timing for Status Flag Clearing by DTC Activation