Renesas H8S/2318 series, Hardware Manual

Page: 669 / 1121

Rev. 5.00, 12/03, page 639 of 1088
in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128
bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 +
α
+
β
)
µ
s as the WDT overflow period. After this, preparation
for program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after
the elapse of (y)
µ
s or more, the operating mode is switched to program mode by setting the Pn bit
in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set
the programming time according to the table in the programming flowchart.
17.16.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for
addresses H'040000 to H'07FFFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared to 0, then the PSUn bit is cleared to 0 at least (
α
)
µ
s later). Next, the
watchdog timer is cleared after the elapse of (
β
)
µ
s or more, and the operating mode is switched to
program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode,
a dummy write of H'FF data should be made to the addresses to be read. The dummy write should
be executed after the elapse of (
γ
)
µ
s or more. When the flash memory is read in this state (verify
data is read in 16-bit units), the data at the latched address is read. Wait at least (
ε
)
µ
s after the
dummy write before performing this read operation. Next, the originally written data is compared
with the verify data, and reprogram data is computed (see figure 17-45) and transferred to the
reprogram data area. After 128 bytes of data have been verified, exit program-verify mode and
wait for at least (
η
)
µ
s, then clear the SWEn bit in FLMCRn to 0, and wait again for at least (
θ
)
µ
s. If reprogramming is necessary, set program mode again, and repeat the program/program-
verify sequence as before. However, ensure that the program/program-verify sequence is not
repeated more than (N) times on the same bits.