Rev. 5.00, 12/03, page 948 of 1088
TIOR3L—Timer I/O Control Register 3L
H'FE83
TPU3
0
1
TGR3D I/O Control
0
1
0
1
0
1
0
1
0
1
×
0
1
0
1
0
1
0
1
0
1
×
×
0
1
TGR3C
is output
compare
register
*
1
TGR3C I/O Control
0
1
0
1
0
1
0
1
0
1
×
0
1
0
1
0
1
0
1
0
1
×
×
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
×
: Don't care
×
: Don't care
Notes:
Note:
*
When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer
register, this setting is invalid and input capture/output compare does not
occur.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
0
IOC0
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Initial output is
0 output
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
Initial output is 1
output
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
source is
TIOCC3 pin
TGR3C
is input
capture
register
*
Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
TGR3D
is output
compare
register
*
2
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
Initial output is 0
output
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
Initial output is 1
output
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
source is
TIOCD3 pin
TGR3D
is input
capture
register
*
2
Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
*
1
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and
φ
/1 is used as
the TCNT4 count clock, this setting is invalid and input capture does not
occur.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer
register, this setting is invalid and input capture/output compare does not
occur.
Summary of Contents for H8S/2318 series
Page 2: ......
Page 6: ...Rev 5 00 12 03 page vi of xxx...
Page 12: ...Rev 5 00 12 03 page xii of xxx...
Page 30: ...Rev 5 00 12 03 page xxx of xxx...
Page 54: ...Rev 5 00 12 03 page 24 of 1088...
Page 98: ...Rev 5 00 12 03 page 68 of 1088...
Page 128: ...Rev 5 00 12 03 page 98 of 1088...
Page 138: ...Rev 5 00 12 03 page 108 of 1088...
Page 168: ...Rev 5 00 12 03 page 138 of 1088...
Page 212: ...Rev 5 00 12 03 page 182 of 1088...
Page 324: ...Rev 5 00 12 03 page 294 of 1088...
Page 436: ...Rev 5 00 12 03 page 406 of 1088...
Page 546: ...Rev 5 00 12 03 page 516 of 1088...
Page 580: ...Rev 5 00 12 03 page 550 of 1088...
Page 822: ...Rev 5 00 12 03 page 792 of 1088...
Page 876: ...Rev 5 00 12 03 page 846 of 1088...
Page 901: ...Rev 5 00 12 03 page 871 of 1088 A 2 Instruction Codes Table A 2 shows the instruction codes...
Page 1121: ...H8S 2319 Group H8S 2318 Group Hardware Manual REJ09B0089 0500O...
