Renesas H8S/2318 series, Hardware Manual

Page: 1011 / 1121

Rev. 5.00, 12/03, page 981 of 1088
SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator
7
PSTOP
0
R/W
6

0
R/W
5
DIV
0
R/W
4

0

3

0

0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
1
PSTOP Normal Operation
φ
output
Fixed high
High impedance
High impedance
Fixed high
Fixed high
φ
Clock Output Control
System Clock Select
Division
Ratio
Select
Reserved
Only 0 should be
written to this bit
0
1
0
1
0
1
0
1
0
1
0
1

Bus master is in high-speed mode
Medium-speed clock is
φ
/2
Medium-speed clock is
φ
/4
Medium-speed clock is
φ
/8
Medium-speed clock is
φ
/16
Medium-speed clock is
φ
/32

Bus master is in high-speed mode
Clock supplied to entire chip is
φ
/2
Clock supplied to entire chip is
φ
/4
Clock supplied to entire chip is
φ
/8



φ
output
Fixed high
Sleep Mode
Bit
Initial value
Read/Write
:
:
:
Software
Standby Mode
Hardware
Standby Mode
DIV = 0 DIV = 1