Renesas H8S/2318 series, Hardware Manual

Page: 419 / 1121

Rev. 5.00, 12/03, page 389 of 1088
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0
Description
0 0 0 Clock input disabled (Initial value)
1 Internal clock, counted at falling edge of
φ
/8
1 0 Internal clock, counted at falling edge of
φ
/64
1 Internal clock, counted at falling edge of
φ
/8192
1 0 0 For channel 0: count at TCNT1 overflow signal
*
For channel 1: count at TCNT0 compare match A
*
1 External clock, counted at rising edge
1 0 External clock, counted at falling edge
1 External clock, counted at both rising and falling edges
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
TCSR0
Bit : 7 6 5 4 3 2 1 0
CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)
*
R/(W)
*
R/(W)
*
R/W R/W R/W R/W R/W
TCSR1
Bit : 7 6 5 4 3 2 1 0
CMFB CMFA OVF — OS3 OS2 OS1 OS0
Initial value : 0 0 0 1 0 0 0 0
R/W : R/(W)
*
R/(W)
*
R/(W)
*
— R/W R/W R/W R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and
control compare match output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.