Renesas H8S/2318 series, Hardware Manual

Page: 406 / 1121

Rev. 5.00, 12/03, page 376 of 1088
Contention between TGR Write and Compare Match: If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 9-51 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N+1
Inhibited
Figure 9-51 Contention between TGR Write and Compare Match