Renesas H8S/2318 series, Hardware Manual

Page: 133 / 1121

Rev. 5.00, 12/03, page 103 of 1088
Address bus
Vector fetch
Internal
processing Prefetch of first
program instruction
(1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
(2), (4) Start address (contents of reset exception vector address)
(5)
Start address ((5) = (2), (4))
(6) First program instruction
φ
RES
(1) (5)
High
(2) (4)
(3)
(6)
RD
HWR
,
LWR
D
15
to D
0
*
Note:
*
3 program wait states are inserted.
* *
Figure 4-2 Reset Sequence (Mode 4)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.4 State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DTC enter
module stop mode. Consequently, on-chip supporting module registers cannot be read or written
to. Register reading and writing is enabled when module stop mode is exited.