Renesas H8S/2318 series, Hardware Manual

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Rev. 5.00, 12/03, page 525 of 1088
Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D
conversion time. See the description of the CKS bit for details.
Bit 2—Reserved: A value of 1 must be written to this bit.
14.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode.
Bit 9
MSTP9
Description
0 A/D converter module stop mode cleared
1 A/D converter module stop mode set (Initial value)