Rev. 5.00, 12/03, page 673 of 1088
17.22.8
Pin Configuration
Flash memory is controlled by the pin as shown in table 17-47.
Table 17-47 Pin Configuration
Pin Name
Abbreviation
Input/Output
Function
Reset
RES
Input
Reset
Mode 2
MD2
Input
Sets operating mode of this LSI
Mode 1
MD1
Input
Sets operating mode of this LSI
Mode 0
MD0
Input
Sets operating mode of this LSI
Port 66
P66
Input
Sets operating mode of this LSI in
PROM Mode
Port 65
P65
Input
Sets operating mode of this LSI in
PROM Mode
Port 64
P64
Input
Sets operating mode of this LSI in
PROM Mode
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
Note:
For the pin configuration in PROM mode, see section 17.28, PROM Mode.
17.22.9
Register Configuration
(1) Registers
The registers/parameters which control flash memory when the on-chip flash memory is valid are
shown in table 17-48.
To access any of the flash memory control registers except RAMER, the FLSHE bit in SYSCR2
must be set to 1 in a mode in which flash memory is enabled.
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 17-49.
Summary of Contents for H8S/2318 series
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